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  1 of 338 rev: 072105 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the DS33R11 extends a 10/100 ethernet lan segment by encapsulating mac frames in hdlc or x.86 (laps) for transmission over a t1/e1/j1 data stream. the device performs store-and-forward of packets with full wire-speed transport capability. the built-in committed information rate (cir) controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. the DS33R11 can operate with an inexpensive external processor. applications transparent lan service lan extension ethernet delivery over t1/e1/j1 functional diagram features  10/100 ieee 802.3 ethernet mac (mii and rmii) half/full duplex with automatic flow control  integrated t1/e1/j1 framer and liu  hdlc/laps encapsulation with programmable fcs and interframe fill  committed information rate controller provides fractional allocations in 512kbps increments  programmable bert for serial (tdm) interface  external 16mb, 100mhz sdram buffering  parallel microprocessor interface  1.8v, 3.3v supplies  reference design routes on two signal layers  ieee 1149.1 jtag support features continued on page 11 . ordering information part temp range pin-package DS33R11 -40c to +85c 256 bga DS33R11 ethernet mapper with integrated t1/e1/j1 transceive r www.maxim-ic.com 10/100 mac sdram mii/rmii  c DS33R11 10/100 ethernet phy serial stream t1/e1/j1 transceiver bert hdlc/x.86 mapper t1/e1 line
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 2 of 338 table of contents 1 description .................................................................................................................... ...........9 2 feature highlights ............................................................................................................. .11 2.1 g eneral ............................................................................................................................... ...11 2.2 m icroprocessor i nterface ..................................................................................................11 2.3 hdlc e thernet m apping .......................................................................................................11 2.4 x.86 (l ink a ccess p rotocol for sonet/sdh) e thernet m apping ....................................11 2.5 a dditional hdlc c ontrollers in the integrated t1/e1/j1 t ransceiver ..........................12 2.6 c ommitted i nformation r ate (cir) c ontroller ..................................................................12 2.7 sdram i nterface ..................................................................................................................12 2.8 mac i nterface .......................................................................................................................12 2.9 t1/e1/j1 l ine i nterface .........................................................................................................13 2.10 c lock s ynthesizer ................................................................................................................13 2.11 j itter a ttenuator .................................................................................................................13 2.12 t1/e1/j1 f ramer ....................................................................................................................14 2.13 tdm b us ............................................................................................................................... ..14 2.14 t est and d iagnostics ............................................................................................................15 2.15 s pecifications c ompliance ...................................................................................................16 3 applications ................................................................................................................... ........17 4 acronyms and glossary....................................................................................................18 5 major operating modes.....................................................................................................19 6 block diagrams................................................................................................................. ....20 7 pin descriptions............................................................................................................... .....25 7.1 p in f unctional d escription ..................................................................................................25 8 function al descri ption .....................................................................................................41 8.1 processor interface ....................................................................................................42 8.1.1 read-write / data strobe modes ................................................................................................. .......42 8.1.2 clear on read .................................................................................................................. ...................42 8.1.3 interrupt and pin modes ........................................................................................................ ..............42 9 ethernet mapper ................................................................................................................ ..43 9.1 e thernet m apper c locks .....................................................................................................43 9.1.1 ethernet interface clock modes ................................................................................................. .........45 9.1.2 serial interface clock modes ................................................................................................... ...........45 9.2 r esets and l ow p ower m odes .............................................................................................46 9.3 i nitialization and c onfiguration ..........................................................................................47 9.4 g lobal r esources ................................................................................................................47 9.5 p er -p ort r esources ............................................................................................................47 9.6 d evice i nterrupts .................................................................................................................48 9.7 i nterrupt i nformation r egisters ........................................................................................50 9.8 s tatus r egisters ..................................................................................................................50 9.9 i nformation r egisters ..........................................................................................................50 9.10 s erial i nterface ....................................................................................................................50 9.11 c onnections and q ueues ......................................................................................................51 9.12 a rbiter ............................................................................................................................... ....52 9.13 f low c ontrol ........................................................................................................................53 9.13.1 full duplex flow control ....................................................................................................... ..............54 9.13.2 half duplex flow control....................................................................................................... ..............55 9.13.3 host-managed flow control...................................................................................................... ..........55
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 3 of 338 9.14 e thernet i nterface p ort ......................................................................................................56 9.14.1 dte and dce mode............................................................................................................... .............58 9.15 e thernet mac .......................................................................................................................59 9.15.1 mii mode options ............................................................................................................... .................61 9.15.2 rmii mode...................................................................................................................... .....................61 9.15.3 phy mii management block and mdio interface...............................................................................62 9.16 bert in the e thernet m apper ..............................................................................................62 9.16.1 receive data interface......................................................................................................... ...............63 9.16.2 repetitive pattern synchronization ............................................................................................. ........64 9.16.3 pattern monitoring ............................................................................................................. ..................64 9.16.4 pattern generation ............................................................................................................. .................64 9.17 t ransmit p acket p rocessor ................................................................................................65 9.18 r eceive p acket p rocessor ..................................................................................................66 9.19 x.86 e ncoding and d ecoding ................................................................................................68 9.20 committed information rate controller .............................................................71 10 integrated t1/e1/j1 transceiver .....................................................................................72 10.1 t1/e1/j1 c locks ....................................................................................................................72 10.2 p er -c hannel o peration ........................................................................................................73 10.3 t1/e1/j1 t ransceiver i nterrupts ........................................................................................73 10.4 t1 framer/formatter control and status ...........................................................74 10.4.1 t1 transmit transparency ....................................................................................................... ...........74 10.4.2 ais-ci and rai-ci gener ation and detection ..................................................................................... 74 10.4.3 t1 receive-side digital-m illiwatt code g eneration ............................................................................75 10.5 e1 f ramer /f ormatter c ontrol and s tatus ........................................................................76 10.5.1 automatic alar m generation ..................................................................................................... ..........77 10.6 p er -c hannel l oopback .........................................................................................................77 10.7 e rror c ounters ....................................................................................................................78 10.7.1 line-code violation c ounter (tr.lcvcr)......................................................................................... .78 10.7.2 path code violation count register (tr.pcvcr)..............................................................................79 10.7.3 frames out-of-sync count register (tr.foscr) .............................................................................80 10.7.4 e-bit counter (tr.ebcr)........................................................................................................ ............80 10.8 ds0 m onitoring f unction .....................................................................................................81 10.9 s ignaling o peration ..............................................................................................................82 10.9.1 processor-based re ceive si gnaling.............................................................................................. .....82 10.9.2 hardware-based re ceive si gnaling............................................................................................... .....83 10.9.3 processor-based transmit signaling............................................................................................. .....84 10.9.4 hardware-based tr ansmit si gnaling.............................................................................................. .....85 10.10 p er -c hannel i dle c ode g eneration .....................................................................................86 10.10.1 idle-code progra mming exam ples ................................................................................................. ....87 10.11 c hannel b locking r egisters ................................................................................................88 10.12 e lastic s tores o peration ....................................................................................................88 10.12.1 receive elas tic store .......................................................................................................... ................88 10.12.2 transmit elastic store ......................................................................................................... ................89 10.12.3 elastic stores initializ ation.................................................................................................. .................89 10.12.4 minimum de lay mode............................................................................................................. .............89 10.13 g.706 i ntermediate crc-4 u pdating (e1 m ode o nly ) .........................................................90 10.14 t1 b it -o riented c ode (boc) c ontroller ............................................................................91 10.14.1 transmit boc................................................................................................................... ...................91 10.15 r eceive boc ..........................................................................................................................91 10.16 a dditional (s a ) and i nternational (s i ) b it o peration (e1 o nly ) ........................................92 10.16.1 method 1: internal register scheme based on d ouble-frame...........................................................92 10.16.2 method 2: internal register sc heme based on crc4 multiframe ......................................................92 10.17 a dditional hdlc c ontrollers in t1/e1/j1 t ransceiver ....................................................93 10.17.1 hdlc configuration ............................................................................................................. ...............93 10.17.2 fifo control................................................................................................................... .....................95
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 4 of 338 10.17.3 hdlc mapping................................................................................................................... .................95 10.17.4 fifo information ............................................................................................................... ..................96 10.17.5 receive packet-by tes available ................................................................................................. ........96 10.18 l egacy fdl s upport (t1 m ode )............................................................................................97 10.18.1 overview ....................................................................................................................... ......................97 10.18.2 receive se ction ................................................................................................................ ..................97 10.18.3 transmit section ............................................................................................................... ..................98 10.19 d4/slc-96 o peration ............................................................................................................98 10.20 p rogrammable i n -b and l oop c ode g eneration and d etection ..........................................99 10.21 l ine i nterface u nit (liu) ..................................................................................................... 100 10.21.1 liu operation .................................................................................................................. ..................100 10.21.2 receiver ....................................................................................................................... .....................100 10.21.3 transmitter .................................................................................................................... ....................102 10.22 mclk p rescaler ................................................................................................................. 103 10.23 j itter a ttenuator ............................................................................................................... 103 10.24 cmi (c ode m ark i nversion ) o ption .................................................................................... 103 10.25 r ecommended c ircuits ........................................................................................................ 104 10.26 t1/e1/j1 transcei ver bert f unction ........................................................................ 108 10.26.1 bert status.................................................................................................................... ..................108 10.26.2 bert mapping ................................................................................................................... ...............108 10.26.3 bert repetitive pattern set.................................................................................................... .........110 10.26.4 bert bit counter............................................................................................................... ...............110 10.26.5 bert error counter ............................................................................................................. .............110 10.26.6 bert alternating word-count rate ............................................................................................... ..110 10.27 p ayload e rror -i nsertion f unction (t1 m ode o nly )......................................................... 111 10.27.1 number-of-errors registers ..................................................................................................... .........111 10.28 p rogrammable b ackplane c lock s ynthesizer .................................................................. 112 10.29 f ractional t1/e1 s upport .................................................................................................. 112 10.30 t1/e1/j1 t ransmit f low d iagrams ..................................................................................... 113 11 device registers............................................................................................................... .. 117 11.1 r egister b it m aps ................................................................................................................ 118 11.1.1 global ethernet mapper register bit map........................................................................................ .118 11.1.2 arbiter register bit map ....................................................................................................... .............119 11.1.3 bert register bit map .......................................................................................................... ...........119 11.1.4 serial interface r egister bit map.............................................................................................. .........120 11.1.5 ethernet interface register bit map ............................................................................................ ......122 11.1.6 mac register bit map........................................................................................................... ............123 11.2 g lobal r egister d efinitions for e thernet m apper ......................................................... 130 11.3 a rbiter r egisters ............................................................................................................... 139 11.3.1 arbiter register bit descriptions .............................................................................................. .........139 11.4 bert r egisters .................................................................................................................. 140 11.5 s erial i nterface r egisters ................................................................................................ 147 11.5.1 serial interface transmi t and common registers ............................................................................147 11.5.2 serial interface transmit r egister bit de scriptions...........................................................................1 47 11.5.3 transmit hdlc processor registers .............................................................................................. ..148 11.5.4 x.86 registers................................................................................................................. ..................155 11.5.5 receive serial interface ....................................................................................................... .............157 11.6 e thernet i nterface r egisters ........................................................................................... 170 11.6.1 ethernet interface register bit descriptions ................................................................................... ..170 11.6.2 mac registers .................................................................................................................. ................182 11.7 t1/e1/j1 t ransceiver r egisters ........................................................................................ 197 11.7.1 number-of-errors left register................................................................................................. ........293 12 functional timi ng .............................................................................................................. . 294 12.1 f unctional s erial i/o t iming ............................................................................................... 294
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 5 of 338 12.2 mii and rmii i nterfaces ...................................................................................................... 295 12.3 t ransceiver t1 m ode f unctional t iming ........................................................................... 297 12.4 e1 m ode ............................................................................................................................... 302 13 operating parameters ..................................................................................................... 307 13.1 t hermal c haracteristics ................................................................................................... 308 13.2 mii i nterface ........................................................................................................................ 309 13.3 rmii i nterface ..................................................................................................................... 311 13.4 mdio i nterface ................................................................................................................... 313 13.5 t ransmit wan i nterface .................................................................................................... 314 13.6 r eceive wan i nterface ...................................................................................................... 315 13.7 sdram t iming ...................................................................................................................... 316 13.8 m icroprocessor b us ac c haracteristics ........................................................................ 318 13.9 ac c haracteristics : r eceive -s ide ..................................................................................... 321 13.10 ac c haracteristics : b ackplane c lock t iming .................................................................. 325 13.11 ac c haracteristics : t ransmit s ide ................................................................................... 326 13.12 jtag i nterface t iming ........................................................................................................ 329 14 jtag information ............................................................................................................... . 330 14.1 jtag tap c ontroller s tate m achine d escription .......................................................... 331 14.2 i nstruction r egister .......................................................................................................... 333 14.3 jtag id c odes ..................................................................................................................... 335 14.4 t est r egisters .................................................................................................................... 335 14.4.1 boundary scan register ......................................................................................................... ..........335 14.4.2 bypass register ................................................................................................................ ................335 14.4.3 identificati on register........................................................................................................ ................335 14.5 jtag f unctional t iming ...................................................................................................... 336 15 package information ........................................................................................................ 337 15.1 p ackage o utline d rawing of 256-bga (v iew from b ottom of d evice ) ........................... 337 16 revision history............................................................................................................... ... 338
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 6 of 338 list of figures figure 3-1. ethernet-to-wan extens ion (with or without framing) ................................................................ ......... 17 figure 6-1. main block diagram ................................................................................................. ............................... 20 figure 6-2. block diagram of t1/e1/j1 transceiver.............................................................................. .................... 21 figure 6-3. receive and tr ansmit t1/e1/j1 liu .................................................................................. ..................... 22 figure 6-4. receive and tr ansmit t1/e1/j1 framer ............................................................................... .................. 23 figure 6-5. t1/e1/j1 backplane interface ....................................................................................... .......................... 24 figure 7-1. 256- ball bga pinout................................................................................................ ................................ 40 figure 9-1. clocking for the DS33R11 ........................................................................................... ............................ 44 figure 9-2. device interrupt information flow diagram .......................................................................... ................... 49 figure 9-3. flow control using pause control frame ............................................................................. .................. 55 figure 9-4. ieee 802. 3 ethernet frame .......................................................................................... .......................... 56 figure 9-5. configured as dte connect ed to an ethernet ph y in mii mode......................................................... ... 58 figure 9-6. DS33R11 configured as a dce in mii mode ............................................................................ .............. 59 figure 9-7. rmii interface ..................................................................................................... ..................................... 61 figure 9-8. mii management frame ............................................................................................... ........................... 62 figure 9-9. prbs synchr onization state diagram ................................................................................. ................... 63 figure 9-10. repetitive pattern synchronization state diagram.................................................................. .............. 64 figure 9-11. hdlc encapsulation of mac frame................................................................................... .................. 67 figure 9-12. laps encoding of mac frames concept............................................................................... .............. 68 figure 9-13. x.86 encapsulat ion of the mac frame ............................................................................... ................... 69 figure 10-1. t1/e1/j1 clock map ................................................................................................ .............................. 72 figure 10-2. simplified diagram of receive signaling path ...................................................................... ................ 82 figure 10-3. simplified diagram of transmit signaling path ..................................................................... ................ 84 figure 10-4. crc-4 recalculate method.......................................................................................... ......................... 90 figure 10-5. typical m onitor application....................................................................................... ........................... 101 figure 10-6. cmi coding........................................................................................................ .................................. 103 figure 10-7. basic interface................................................................................................... .................................. 104 figure 10-8. e1 transmit pulse template ........................................................................................ ....................... 105 figure 10-9. t1 transmit pulse template ........................................................................................ ....................... 105 figure 10-10. jitter tolerance................................................................................................. ................................. 106 figure 10-11. jitter to lerance (e1 mode) ....................................................................................... ......................... 106 figure 10-12. jitter a ttenuation (t1 mode) ..................................................................................... ......................... 107 figure 10-13. jitter a ttenuation (e1 mode) ..................................................................................... ......................... 107 figure 10-14. optional crystal connections ..................................................................................... ....................... 108 figure 10-15. simplified diagram of bert in network direction .................................................................. .......... 109 figure 10-16. simplified diagram of bert in backpl ane direction................................................................ ......... 109 figure 10-17. t1/j1 transmit flow diagram ...................................................................................... ..................... 113 figure 10-18. e1 transmit flow diagram ......................................................................................... ....................... 115 figure 12-1. tx serial in terface functional timing............................................................................. ..................... 294 figure 12-2. rx serial in terface functional timing ............................................................................. .................... 294 figure 12-3. transmit byte sync functi onal timing .............................................................................. .................. 295 figure 12-4. receive byte sync functional timing ............................................................................... .................. 295 figure 12-5. mii transmi t functional timing .................................................................................... ....................... 295 figure 12-6. mii transmit half duplex with a collision functional timing ....................................................... ....... 296 figure 12-7. mii receiv e functional timing ..................................................................................... ....................... 296 figure 12-8. rmii transmit in terface functional timing ......................................................................... ................ 296 figure 12-9. rmii receive in terface functional timing .......................................................................... ................ 297 figure 12-10. receive-side d4 timing........................................................................................... ......................... 297 figure 12-11. receiv e-side esf timing .......................................................................................... ....................... 297 figure 12-12. receive-side boundary ti ming (elastic st ore disabled) ............................................................ ...... 298 figure 12-13. receive-side 1.544mhz boundar y timing (elastic store enabled) .................................................. 29 8 figure 12-14. receive-side 2.048mhz boundar y timing (elastic store enabled) .................................................. 29 9 figure 12-15. transmit-side d4 timing.......................................................................................... ......................... 299 figure 12-16. transmit-side esf timing ......................................................................................... ....................... 300 figure 12-17. transmit-side boundary timi ng (with elastic store disabled) ...................................................... .... 300 figure 12-18. transmit-side 1.544mhz boundar y timing (elastic store enabled)................................................. 30 1
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 7 of 338 figure 12-19. transmit-side 2.048mhz boundar y timing (elastic store enabled)................................................. 30 1 figure 12-20. receive-side timing .............................................................................................. ........................... 302 figure 12-21. receive-side boundary timi ng (with elastic store disabled) ....................................................... .... 302 figure 12-22. receive-side boundary timing, rsysclk = 1.544mhz (e -store enabled) .................................... 303 figure 12-23. receive-side boundary timing, rsysclk = 2.048mhz (e -store enabled) .................................... 303 figure 12-24. g.802 timi ng, e1 mode only ....................................................................................... ..................... 304 figure 12-25. transmit-side timing ............................................................................................. ........................... 304 figure 12-26. transmit-side boundary ti ming (elastic st ore disabled) ........................................................... ...... 305 figure 12-27. transmit-side boundary timing, tsys clk = 1.544mhz (elast ic store enabled) .......................... 305 figure 12-28. transmit-side boundary timing, tsys clk = 2.048mhz (elast ic store enabled) ........................... 306 figure 13-1. transmit mii interface timing..................................................................................... ......................... 309 figure 13-2. receive mii interface timing...................................................................................... ......................... 310 figure 13-3. transmit rmii interface timing .................................................................................... ....................... 311 figure 13-4. receive rmii interface timing ..................................................................................... ....................... 312 figure 13-5. mdio interface timing ............................................................................................. ........................... 313 figure 13-6. transmit wan interface timing ..................................................................................... ..................... 314 figure 13-7. receive wan interface timing ...................................................................................... ..................... 315 figure 13-8. sdram interface timing............................................................................................ ......................... 317 figure 13-9. intel bus r ead timing (mod ec = 00) ................................................................................ ................ 319 figure 13-10. intel bus wr ite timing (modec = 00) .............................................................................. ................ 319 figure 13-11. motorola bus read timing (modec = 01) ............................................................................ ........... 320 figure 13-12. motorola bus write timing (modec = 01) ........................................................................... ............ 320 figure 13-13. receive-side timing .............................................................................................. ........................... 322 figure 13-14. receive-side timi ng, elastic st ore enabled ....................................................................... .............. 323 figure 13-15. receive line interface timing .................................................................................... ....................... 324 figure 13-16. receive timi ng delay rclko to bpclk .............................................................................. ........... 325 figure 13-17. transmit-side timing ............................................................................................. ........................... 327 figure 13-18. transmit-side timi ng, elastic st ore enabled...................................................................... .............. 328 figure 13-19. transmit line interface timing................................................................................... ....................... 328 figure 13-20. jtag interface timing diagram.................................................................................... .................... 329 figure 14-1. jtag func tional bloc k diagram ..................................................................................... .................... 330 figure 14-2. tap controller state diagram ...................................................................................... ....................... 333 figure 14-3. jtag functional timing............................................................................................ .......................... 336
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 8 of 338 list of tables table 2-1. t1-related teleco mmunications s pecificat ions ........................................................................ .............. 16 table 7-1. detail ed pin descr iptions........................................................................................... ............................... 25 table 9-1. clocking options for the ethernet interface......................................................................... ..................... 43 table 9-2. reset functions..................................................................................................... ................................... 46 table 9-3. registers rela ted to connecti ons and queues......................................................................... ............... 52 table 9-4. options for flow control ............................................................................................ ............................... 53 table 9-5. registers related to setting the ethernet port...................................................................... ................... 57 table 9-6. mac control registers ............................................................................................... .............................. 60 table 9-7. mac status registers ................................................................................................ .............................. 60 table 10-1. t1/e1/j1 transmit clock source..................................................................................... ....................... 73 table 10-2. t1 alarm criteria.................................................................................................. ................................... 75 table 10-3. e1 sync/resync criteria ............................................................................................ ............................. 76 table 10-4. e1 alarm criteria .................................................................................................. .................................. 77 table 10-5 t1 line code vi olation count ing options............................................................................. ................... 78 table 10-6. e1 line-code vi olation count ing options ............................................................................ .................. 78 table 10-7. t1 path code vi olation counti ng arrangements....................................................................... ............. 79 table 10-8. t1 frames out- of-sync counti ng arrangements ........................................................................ ........... 80 table 10-9. time slot numbering schemes........................................................................................ ...................... 85 table 10-10. idle-code a rray address mapping................................................................................... ..................... 86 table 10-11. elastic store de lay after init ializat ion .......................................................................... ......................... 89 table 10-12. hdlc controller registers ......................................................................................... .......................... 94 table 10-13. transform er specif ications........................................................................................ ......................... 104 table 10-14. transmit erro r-insertion se tup sequence ........................................................................... ............... 111 table 10-15. error insertion examples .......................................................................................... .......................... 111 table 11-1. register address map ............................................................................................... ........................... 117 table 11-2. global ethernet mapper register bit map ............................................................................ ................ 118 table 11-3. arbiter register bit map........................................................................................... ............................. 119 table 11-4. bert register bit map.............................................................................................. ........................... 119 table 11-5. serial interf ace register bit map .................................................................................. ........................ 120 table 11-6. ethernet interface register bit map................................................................................ ...................... 122 table 11-7. mac indirect register bit map ...................................................................................... ....................... 123 table 11-8. t1/e1/j1 transceiver register bit map (active when cst = 0) ........................................................... 125 table 13-1. recommended dc operating conditions ................................................................................ ............ 307 table 13-2. dc electric al characteristics ...................................................................................... .......................... 307 table 13-3. thermal characteristics............................................................................................ ............................ 308 table 13-4. theta-ja vs. airflow............................................................................................... ............................... 308 table 13-5. transmit mii interface............................................................................................. .............................. 309 table 13-6. receive mii interface.............................................................................................. .............................. 310 table 13-7. transmit rmii interface ............................................................................................ ............................ 311 table 13-8. receive rmii interface ............................................................................................. ............................ 312 table 13-9. mdio interface ..................................................................................................... ................................ 313 table 13-10. transmit wan interface ............................................................................................ ......................... 314 table 13-11. receive wan interface ............................................................................................. ......................... 315 table 13-12. sdram interface timing............................................................................................ ........................ 316 table 13-13. ac characteristi cs?microprocessor bus timing ...................................................................... ........ 318 table 13-14. ac characte ristics: re ceive side.................................................................................. ..................... 321 table 13-15. ac characteristi cs: backplane cl ock synt hesis ..................................................................... ........... 325 table 13-16. ac characte ristics: transmit side................................................................................. ..................... 326 table 13-17. jtag interface timing............................................................................................. ........................... 329 table 14-1. instruction codes for ieee 1149.1 architecture ..................................................................... .............. 334 table 14-2. id code structure .................................................................................................. ............................... 335
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 9 of 338 1 description the DS33R11 provides interconnection and mapping functiona lity between ethernet packet systems and t1/e1/j1 wan time-division multiplexed (tdm) systems. the device is composed of a 10/100 ethernet mac, packet arbiter, committed information rate controller (cir), hdlc/x.86 (laps) mapper, sdram interface, control ports, bit error rate tester (bert), and integrated t1/e1/j1 transceiver. the packet interface consists of a mii/rmii ethernet phy interface. the ethernet interface can be configured for 10mbit/s or 100mbit/s service. the DS33R11 encapsulates ethernet traffic with hdlc or x.86 (laps) encoding to be transmitted over a t1, e1, or j1 line. the t1/e1/j1 interface also receives encapsulated ethernet packets and transmits the extracted packets over the ethernet ports. access is provided to the signals between t he serial port and the integrated t1/e1/j1 transceiver. the device includes a software-selectable t1, e1, or j1 single-chip transceiver (sct) for short-haul and long-haul applications. the transceiver is composed of an liu, fr amer, and two additional hdlc controllers. the transceiver is software compatible with the ds2155 and ds2156. the liu is composed of transmit and receive interfaces and a jitter attenuator. the transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. t1 waveform generation includes dsx-1 line build-outs as well as csu line build-outs of -7.5db, -15db, and -22.5db. e1 waveform generation includes g.703 waveshapes for both 75  coax and 120  twisted cables. the receive interface provides network termination and recovers clock and data from the network. the receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43db or 0 to 12db for e1 applications and 0 to 30db or 0 to 36db for t1 applications. the jitter attenuator removes phase jitter from the transmitted or received signal. the crystal-less jitter attenuator requires only a 2.048mhz mclk for both e1 and t1 applications (with the option of using a 1.544mhz mclk in t1 applications) and can be placed in either transmit or receive data paths. an additional featur e of the liu is a cmi coder/decoder for interfacing to optical networks. on the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. the framer inserts the appropriate synchronizati on framing patterns, alarm information, calculates and inserts the crc codes, and provides the b8zs/hdb3 (zer o code suppression) and ami line coding. the receive- side framer decodes ami, b8zs, and hdb3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/crc errors, and provides clock/dat a and frame-sync signals to the backplane interface section. diagnostic capabilities include loopbacks, prbs pattern generation/detection, and 16-bit loop-up and loop- down code generation and detection. both the transmit and receive path have two hdlc controllers. the hdlc controllers transmit and receive data through the framer block. the hdlc controllers can be assigned to any time slot, group of time slots, portion of a time slot or to fdl (t1) or sa bits (e1). each controller has 128-byte fifos, thus reducing the amount of processor overhead required to manage the flow of data. in addition, built-in support for reducing the processor time is required in ss7 applications. the backplane interface provides a versatile method of sending and receiving data from the host system. elastic stores provide a method for interfacing to asynchronous systems, converting from a t1/e1 network to a 2.048mhz, 4.096mhz, 8.192mhz, or n x 64khz system backplane. the elastic stores also manage slip conditions (asynchronous interface). an 8-bit parallel microcontroller port provides access for control and configuration of all the features of the device. the internal 100mhz sdram controller interfaces to a 32-bit wide 128mb sdram. the sdram is used to buffer the data from the ethernet and wan ports for transport. the external sdram can accommodate up to 8192 frames with a maximum frame size of 2016 bytes. diagnostic capabilities include sdram bist, loopbacks, prbs pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. the DS33R11 operates with a 1.8v core supply and 3.3v i/o supply.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 10 of 338 the integrated ethernet mapper is software compatible with the ds33z11 ethernet mapper. there are a few things to note when porting a ds33z11 application to this device:  the spi and hardware modes are not supported.  rser has been renamed to rseri.  rclk has been renamed to rclki.  tser has been renamed to tsero.  tclk has been renamed to tclke. the integrated t1/e1/j1 transceiver is software compatible with the ds2155 t1/e1/j1 transceiver. there are a few things to note when porting a ds2155 application to this device:  the facilities data link (fdl) support is available through software only. the tlink, rlink, tlclk, rlclk pins are not available on the DS33R11.  multiplexed microprocessor bus mode is not supported on the DS33R11.  the extended system information bus (esib) is not supported on the DS33R11.  the modec pins serve the function of the ds2155?s bts pin.  the interim liu/framer clock signals rclki, rcl ko have been renamed to rdclki, rdclko to avoid confusion with the receive clock connections between the transceiver and the ethernet mapper.  the interim liu/framer clock signals tclki, tclk o have been renamed to tdclki, tdclko to avoid confusion with the receive clock connections between the transceiver and the ethernet mapper.  rser has been renamed rsero.  rclk has been renamed rclko.  tser has been renamed tseri.  tclk has been renamed tclkt.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 11 of 338 2 feature highlights 2.1 general  256-pin, 27mm bga package  1.8v and 3.3v supplies  ieee 1149.1 jtag boundary scan  software access to device id and silicon revision  development support includes evaluation kit, dr iver source code, and reference designs  reference design routes on a two-layer pc board  programmable output clocks for fractional t1, e1, h0, and h12 applications 2.2 microprocessor interface  parallel control port with 8-bit data bus  nonmultiplexed intel and motorola timing modes  internal software reset and external hardware reset-input pin  supports polled or interrupt-driven environments  software access to device id and silicon revision  global interrupt-output pin 2.3 hdlc ethernet mapping  dedicated hdlc controller engine for protocol encapsulation  compatible with polled or interrupt driven environments  programmable fcs insertion and extraction  programmable fcs type  supports fcs error insertion  programmable packet size limits (minimum 64 bytes and maximum 2016 bytes)  supports bit stuffing/destuffing  selectable packet scrambling/descrambling (x 43 +1)  separate fcs errored packet and aborted packet counts  programmable inter-frame fill for transmit hdlc 2.4 x.86 (l ink a ccess p rotocol for s onet/sdh) ethernet mapping  programmable x.86 address/control fields for transmit and receive  programmable 2-byte protocol (sapi) field for transmit and receive  32 bit fcs  transmit transparency processing?7e is replaced by 7d, 5e  transmit transparency processing?7d replaced by 7d, 5d  receive rate adaptation (7d, dd) is deleted.  receive transparency processing?7d, 5e is replaced by 7e  receive transparency processing?7d, 5d is replaced by 7d  receive abort sequence the laps packet is dropped if 7d7e is detect  self-synchronizing x 43 +1 payload scrambling.  frame indication due to bad address/control/sapi, fcs error, abort sequence or frame size longer than preset max
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 12 of 338 2.5 additional hdlc controllers in the integrated t1/e1/j1 transceiver  two additional independent hdlc controllers  fast load and unload features for fifos  ss7 support for fisu transmit and receive  independent 128-byte rx and tx buffers with interrupt support  access fdl, sa, or single/multiple ds0 channels  ds0 access includes nx64 or nx56  compatible with polled or interrupt driven environments  bit-oriented code (boc) support 2.6 committed information rate (cir) controller  cir rate controller limits transmission of data from the ethernet interface to the serial interface  cir granularity at 512kbit/s  cir averaging for smoothing traffic peaks 2.7 sdram interface  interface for 128mb, 32-bit-wide sdram  sdram interface speed up to 100mhz  auto refresh timing  automatic precharge  master clock provided to the sdram  no external components required for sdram connectivity 2.8 mac interface  mac port with standard mii (less tx_er) or rmii  10mbps and 100mbps data rates  configurable dte or dce modes  facilitates auto-negotiation by host microprocessor  programmable half and full-duplex modes  flow control for both half-duplex (back-pressure) and full-duplex (pause) modes  programmable maximum mac frame size up to 2016 bytes  minimum mac frame size: 64 bytes  discards frames greater than programmed maximum mac frame size and runt, nonoctet bounded, or bad-fcs frames upon reception  configurable for promiscuous broadcast-discard mode.  programmable threshold for sdram queues to initiate flow control and status indication  mac loopback support for transmit data looped to receive data at the mii/rmii interface
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 13 of 338 2.9 t1/e1/j1 line interface  requires only a 2.048mhz master clock for both e1 and t1 operation with the option to use 1.544mhz for t1 operation  fully software configurable  short-haul and long-haul applications  automatic receive sensitivity adjustments  ranges include 0 to 43db or 0 to 12db for e1 applications and 0 to 13db or 0 to 36db for t1 applications  receive level indication in 2.5db steps from -42.5db to -2.5db  internal receive termination option for 75  , 100  , and 120  lines  internal transmit termination option for 75  , 100  , and 120  lines  monitor application gain settings of 20db, 26db, and 32db  g.703 receive synchronization-signal mode  flexible transmit waveform generation  t1 dsx-1 line build-outs  t1 csu line build-outs of -7.5db, -15db, and -22.5db  e1 waveforms include g.703 waveshapes for both 75  coax and 120  twisted cables  ais generation independent of loopbacks  alternating ones and zeros generation  square-wave output  open-drain output option  nrz format option  transmitter power-down  transmitter 50ma short-circuit limiter with current-limit-exceeded indication  transmit open-circuit-detected indication  line interface function can be completely decoupled from the framer/formatter 2.10 clock synthesizer  output frequencies include 2.048mhz, 4.096mhz, 8.192mhz, and 16.384mhz  derived from recovered receive clock 2.11 jitter attenuator  32-bit or 128-bit crystal-less jitter attenuator  requires only a 2.048mhz master clock for both e1 and t1 operation with the option to use 1.544mhz for t1 operation  can be placed in either the receive or transmit path or disabled  limit trip indication
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 14 of 338 2.12 t1/e1/j1 framer  fully independent transmit and receive functionality  full receive and transmit path transparency  t1 framing formats include d4 (slc-96) and esf  detailed alarm and status reporting with optional interrupt support  large path and line error counters for: o t1: bpv, cv, crc6, and framing bit errors o e1: bpv, cv, crc4, e-bit, and frame alignment errors  timed or manual update modes  ds1 idle code generation on a per-channel basis in both transmit and receive paths o user-defined o digital milliwatt  ansi t1.403-1998 support  rai-ci detection and generation  ais-ci detection and generation  e1ets 300 011 rai generation  g.965 v5.2 link detect  ability to monitor one ds0 channel in both the transmit and receive paths  in-band repeating pattern generators and detectors o three independent generators and detectors o patterns from 1 to 8 bits or 16 bits in length  rcl, rlos, rra, and rais alarms interrupt on change-of-state  flexible signaling support o software or hardware based o interrupt generated on change of signaling data o receive signaling freeze on loss-of-sync, carrier loss, or frame slip  addition of hardware pins to indi cate carrier loss and signaling freeze  automatic rai generation to ets 300 011 specifications  access to sa and si bits  option to extend carrier loss criteria to a 1ms period as per ets 300 233  japanese j1 support o ability to calculate and check crc6 according to the japanese standard o ability to generate yellow alarm according to the japanese standard 2.13 tdm bus  dual two-frame independent receive and transmit elastic stores o independent control and clocking o controlled slip capability with status o minimum delay mode supported  programmable output clocks for fractional t1, e1, h0, and h12 applications  hardware signaling capability o receive signaling reinsertion to a backplane multiframe sync o availability of signaling in a separate pcm data stream o signaling freezing  ability to pass the t1 f-bit position through the elastic stores in the 2.048mhz backplane mode  access to the data streams in between the framer/formatter and the elastic stores  user-selectable synthesized clock output
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 15 of 338 2.14 test and diagnostics  ieee 1149.1 support  programmable on-chip bit error-rate tester (bert)  pseudorandom patterns including qrss  user-defined repetitive patterns  daly pattern  error insertion single and continuous  total bit and errored bit counts  payload error insertion  error insertion in the payload portion of the t1 frame in the transmit path  errors can be inserted over the entire frame or selected channels  insertion options include continuous and absolute number with selectable insertion rates  f-bit corruption for line testing  loopbacks: remote, local, analog, and per-channel loopback
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 16 of 338 2.15 specifications compliance the DS33R11 meets relevant telecommunications specificat ions. the following table provides the specifications and relevant sections that are applicable to the DS33R11. table 2-1. t1-related telecommunications specifications ieee 802.3-2002?csma/cd access method and physical layer specifications. rfc1662?ppp in hdlc-like framing rfc2615?ppp over sonet/sdh x.86?ethernet over laps rmii?industry implementation agreement for ?reduced mii interface,? sept 1997 ansi: t1.403-1995, t1.231?1993, t1.408 at&t: tr54016, tr62411 itu-t: g.703, g.704, g.706, g.736, g.775, g.823, g.932, i.431, o.151, q.161, recommendation i.432?03/93 b-isdn user-network interface?physical layer specification etsi: ets 300 011, ets 300 166, ets 300 233, ctr12, ctr4 japanese: jtg.703, jti.431, jj-20.11 (cmi coding only)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 17 of 338 3 applications the DS33R11 is ideal for application areas such as trans parent lan service, lan extension, and ethernet delivery over t1/e1/j1, t3/e3, oc-1 /ec-1, g.shdsl, or hdsl2/4. for an example of a complete lan-to-wan design, refer to application note 3411: ds33z11?ethernet lan to unframed t1/e1 wan bridge , available on our website at www.maxim-ic.com/telecom . figure 3-1. ethernet-to-wan extension (with or without framing) ethernet DS33R11 rmii, mii 10 base t 100 base t inter-building lan extension t1/e1/j1 stream sdram clock sources
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 18 of 338 4 acronyms and glossary  bert: bit error-rate tester  dce: data communication interface  dte: data terminating interface  fcs: frame check sequence  hdlc: high-level data link control  mac: media access control  mii: media independent interface  rmii: reduced media independent interface  wan: wide area network note 1: previous versions of this document used the term ?subscriber? to refer to the ethernet interface function. the register names have been allowed to remain with a ?su.? prefix to avoid register renaming. note 2: previous versions of this document used the term ?line? to refer to the serial interface. the register names have been allowed to remain with a ?li.? prefix to avoid register renaming. note3 : the terms ?transmit queue? and ?receive queue? are with respect to the ethernet interface. the receive queue is the queue for the data that arrives on the mii/rmii interface, is processed by the mac and stored in the sdram. transmit queue is for data that arrives from the serial port, is processed by the hdlc and stored in the sdram to be sent to the mac transmitter. note 4: this data sheet assumes a particular nomenclature of the t1 operating environment. in each 125  s frame there are 24 8-bit channels plus a framing bit. it is assumed t hat the framing bit is sent first followed by channel 1. each channel is made up of eight bits that are numbered 1 to 8. bit number 1 is the msb and is transmitted first. bit number 8 is the lsb and is transmitted last. the term ?locked? is used to refer to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544mhz clock can be locked to a 2.048mhz clock if they share the same 8khz component). throughout this data sheet, the following abbreviations are used: b8zs bipolar with 8 zero substitution boc bit-oriented code crc cyclical redundancy check d4 superframe (12 frames per multiframe) multiframe structure esf extended superframe (24 frames per multiframe) multiframe structure fdl facility data link fps framing pattern sequence in esf fs signaling framing pattern in d4 ft terminal framing pattern in d4 hdlc high-level data link control mf multiframe slc?96 subscriber loop carrier?96 channels
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 19 of 338 5 major operating modes microprocessor control is possible through the 8-bit para llel control port and provides configuration for all the features of the device. the ethernet link transport engine in the device can be configured for hdlc or x.86 encapsulation. the integrated transceiver can be software configured for t1, e1, or j1 operation. it is composed of a line interface unit (liu), framer, two additional hdlc controllers, and a tdm backplane interface, and is controlled via an 8-bit parallel port configured for intel or motorola bus operations. the lius are composed of a transmit interface, receive interface, and a jitter attenuator. the transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. t1 waveform generation includes dsx-1 line build-outs as well as csu line build-outs of -7.5db, -15db, and -22.5db. e1 waveform generation includes g.703 waveshapes for both 75  coax and 120  twisted cables. the receive interface provides network termination and recovers clock and data from the network. the receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0db to 43db or 0db to 12db for e1 applications and 0db to 15db or 0db to 36db for t1 applications. the jitter attenuator removes phase jitter from the transmitted or received signal. the crystal-less jitter attenuator requires only a 2.048mhz mclk for both e1 and t1 applications (with the option of using a 1.544mhz mclk in t1 applications) and can be placed in either transmit or receive data paths. more information on microprocessor control is available in section 8.1 .
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 20 of 338 6 block diagrams figure 6-1. main block diagram ttip tring rtip rring sysclki (rmii mode) rxd[0:1] rx_clk crs_dv rx_err ref_clk ref_clko tx_en txd[0:1] mdc mdio mclk tdclki tdclko tposi tposo tnegi tnego tchblk tchclk tclkt tseri tsero tclke tden jtag pin s liuc rdclki rdclko rposi rposo rnegi rnego rchbl k rchcl k rclko rsero rseri rclki rden transmit liu receive liu transmit framer receivie framer ethernet mac  p port sdram port c st c s a0-a9 d0-d7 w r r d i nt sdc s sra s sca s sw e sba[0:1] sdata[0:32] sdmask[0:4] sdcl k jtag pin s arbiter cir controller packet hdlc/x.86 packet hdlc/x.86 ethernet mapper t1/e1/j1 transceiver transmit serial port receive serial port jtag2 jtag1 clad mux mux clad bert bert hdlc hdlc note: some pins not shown. the block in th e diagram labeled ?t1/e1/j1 transceiver? is divided into three functional blocks: liu, fr amer, and backplane interf ace outlined in the following diagrams.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 21 of 338 figure 6-2. block diagram of t1/e1/j1 transceiver tx liu clock adapter backplane interface circuit host interface t1/e1/j1 network clock jtag esib rx liu jitter attenuator local loopback remote loopback framer loopback payload loopback mux mux external access to receive signals external access to transmit signals backplane backplane clock synth liu framer backplane interface sync hdlcs singaling alarm det framer crc gen singaling alarm gen hdlcs hdb3 / b8zs hdb3 / b8zs
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 22 of 338 local loopback tring ttip jitter attenuator transmit or receive path receive line i/f rring rtip remote loopback vco / pll mclk 8xclk 32.768mhz xtald rposo rnego rnegi rposi tposi tnegi tnego tposo rdclko rdclki tdclki tdclko liuc mux mux rpos rclk rneg tneg tclk tpos jaclk rcl transmit line i/f internal signals to framer figure 6-3. receive and transmit t1/e1/j1 liu
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 23 of 338 receive framer transmit framer data clock sync sync clock data framer loopback xmit hdlc #1 mapper xmit hdlc #2 mapper 128 byte fifo 128 byte fifo mapper mapper rec hdlc #1 rec hdlc #2 128 byte fifo 128 byte fifo data clock sync sync clock data rpos rneg rclk tpos tneg tclk payload loopback internal signals from liu internal signals to backplane interface figure 6-4. receive and transmit t1/e1/j1 framer
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 24 of 338 figure 6-5. t1/e1/j1 backplane interface rlink rlclk rsig rsigfr rsero rclko rsync rdata rfsync rmsync elastic store signaling buffer sa bit/fdl extraction data clock sync rchblk rchclk channel timing rsysclk tseri tsig tssync tsync tdata teso tchblk tchclk tlink tlclk channel timing sync clock data signaling buffer elastic store sa/fdl insert tclk mux tclkt tsysclk jaclk internal signals from framer
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 25 of 338 7 pin descriptions 7.1 pin functional description note that all digital pins are io pins in jtag mode. this feature increases the effectiveness of board level atpg patterns. legend: i = input, o = output, ipu = input with pullup, oz = output with tri-state, io = bidirectional pin, ioz = bidirectional pin with tri-state. table 7-1. detailed pin descriptions name pin type description microprocessor port a0 a18 i address bit 0: address bit 0 of the microprocessor interface. least significant bit. a1 b18 i address bit 1: address bit 1 of the microprocessor interface. a2 c18 i address bit 2: address bit 2 of the microprocessor interface. a3 a17 i address bit 3: address bit 3 of the microprocessor interface. a4 b17 i address bit 4: address bit 4 of the microprocessor interface. a5 c17 i address bit 5: address bit 5 of the microprocessor interface. a6 a16 i address bit 6: address bit 6 of the microprocessor interface. a7 b16 i address bit 7: address bit 7 of the microprocessor interface. a8 c16 i address bit 8: address bit 8 of the microprocessor interface. a9 c15 i address bit 9: address bit 9 of the microprocessor interface. d0 a14 ioz data bit 0: bidirectional data bit 0 of the microprocessor interface. least significant bit. not driven when cs =1 or rst =0. d1 b14 ioz data bit 1: bidirectional data bit 1 of the microprocessor interface. not driven when cs =1 or rst =0. d2 c14 ioz data bit 2: bidirectional data bit 2 of the microprocessor interface. not driven when cs =1 or rst =0. d3 a13 ioz data bit 3: bidirectional data bit 3 of the microprocessor interface. not driven when cs =1 or rst =0. d4 b13 ioz data bit 4: bidirectional data bit 4 of the microprocessor interface. not driven when cs =1 or rst =0. d5 c13 ioz data bit 5: bidirectional data bit 5 of the microprocessor interface. not driven when cs =1 or rst =0. d6 a12 ioz data bit 6: bidirectional data bit 6 of the microprocessor interface. not driven when cs =1 or rst =0. d7 b12 ioz data bit 7: bidirectional data bit 7 of the microprocessor interface. most significant bit. not driven when cs =1 or rst =0. wr /r w c11 i write (intel mode): the DS33R11 captures the contents of the data bus (d0-d7) on the rising edge of wr and writes them to the addressed register location. cs must be held low during write operations. read write (motorola mode): used to indicate read or write operation. r w must be set high for a register read cycle and low for a register write cycle.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 26 of 338 name pin type description rd / ds b11 i read data strobe (intel mode): the DS33R11 drives the data bus (d0-d7) with the contents of the addressed register while rd and cs are both low. data strobe (motorola mode): used to latch data through the microprocessor interface. ds must be low during read and write operations. cs a11 i chip select for protocol conversion device: this pin must be taken low for read/write operations. when cs is high, the rd / ds and wr signals are ignored. cst d7 i chip select for the t1/e1/j1 transceiver: must be low to read or write the t1/e1/j1 transceiver. int a10 oz interrupt output: outputs a logic zero when an unmasked interrupt event is detected. int is deasserted when all interrupts have been acknowledged and serviced. active low. inactive state is programmable in register gl.cr1 . is deasserted when all interrupts have been acknowledged and serviced. active low. inactive state is programmable in register gl.cr1 .
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 27 of 338 name pin type description mii/rmii phy port col_det n18 o collision detect (mii): asserted by the mac phy to indicate that a collision is occurring. in dce mode this signal should be connected to ground. this signal is only valid in half duplex mode, and is ignored in full duplex mode. rx_crs/ crs_dv m19 i receive carrier sense (mii): should be asserted (high) when data from the phy (rxd[3:0) is valid. for each clock pulse 4 bits arrive from the phy. bit 0 is the least significant bit. in dce mode, connect to v dd . carrier sense/receive data valid (rmii): this signal is asserted (high) when data is valid from the phy. for each clock pulse 2 bits arrive from the phy. in dce mode, this signal must be grounded. rx_clk m20 io receive clock (mii): timing reference for rx_dv, rx_err and rxd[3:0], which are clocked on the rising edge. rx_clk frequency is 25mhz for 100mbit/s operation and 2.5mhz for 10mbit/s operation. in dte mode, this is a clock input provided by the phy. in dce mode, this is an output derived from ref_clk providing 2.5mhz (10mbit/s operation) or 25mhz (100mbit/s operation). rxd[0] l18 rxd[1] l19 rxd[2] l20 rxd[3] m18 o receive data 0 through 3(mii): four bits of received data, sampled synchronously with the rising edge of rx_clk. for every clock cycle, the phy transfers 4 bits to the DS33R11. rxd[0] is the least significant bit of the data. data is not considered valid when rx_dv is low. receive data 0 through 1(rmii): two bits of received data, sampled synchronously with ref_clk with 100mbit/s mode. accepted when crs_dv is asserted. when configured for 10mbit/s mode, the data is sampled once every 10 clock periods. rx_dv k19 i receive data valid (mii): this active high signal indicates valid data from the phy. the data rxd is ignored if rx_dv is not asserted high. rx_err k18 i receive error (mii): asserted by the mac phy for one or more rx_clk periods indicating that an error has occurred. active high indicates receive code group is invalid. if crs_dv is low, rx_err has no effect. this is synchronous with rx_clk. in dce mode, this signal must be grounded. receive error (rmii): signal is synchronous to ref_clk. tx_clk h19 io transmit clock (mii): timing reference for tx_en and txd[3:0]. the tx_clk frequency is 25mhz for 100mbit/s operation and 2.5mhz for 10mbit/s operation. in dte mode, this is a clock input provided by the phy. in dce mode, this is an output derived from ref_clk providing 2.5mhz (10mbit/s operation) or 25mhz (100mbit/s operation).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 28 of 338 name pin type description txd[0] f19 txd[1] f18 txd[2] e20 txd[3] e19 o transmit data 0 through 3(mii): txd [3:0] is presented synchronously with the rising edge of tx_clk. txd [0] is the least significant bit of the data. when tx_en is low the data on txd should be ignored. transmit data 0 through 1(rmii): two bits of data txd [1:0] presented synchronously with the rising edge of ref_clk. tx_en f20 o transmit enable (mii): this pin is asserted high when data txd [3:0] is being provided by the DS33R11. the signal is deasserted prior to the first nibble of the next frame. this signal is synchronous with the rising edge tx_clk. it is asserted with the first bit of the preamble. transmit enable (rmii): when this signal is asserted, the data on txd [1:0] is valid. this signal is synchronous to the ref_clk. ref_clk a19 i reference clock (rmii and mii): when in rmii mode, all signals from the phy are synchronous to this clock input for both transmit and receive. this required clock can be up to 50mhz and should have 100ppm accuracy. when in mii mode in dce operation, the DS33R11 uses this input to generate the rx_clk and tx_clk outputs as required for the ethernet phy interface. when the mii interface is used with dte operation, this clock is not required and should be tied low. ref_clko a20 o reference clock output (rmii and mii): a derived clock output up to 50mhz, generated by internal division of the sysclki signal. frequency accuracy of the ref_clko signal will be proportional to the accuracy of the user-supplied sysclki signal. this output can be used for the rmii/mii interface clock by external connection to ref_clk. this capability eliminates the need for an additional 50 mhz (rmii) or 25mhz (mii) phy reference oscillator. see section 9.1.1 for more information. dcedtes g20 i dce or dte selection: the user must set this pin high for dce mode selection or low for dte mode. in dce mode, the DS33R11 mac port can be directly connected to another mac. in dce mode, the transmit clock (tx_clk) and receive clock (rx_clk) are output by the DS33R11. note that there is no software bit selection of dcedtes. note that dce mode is only relevant when the mac interface is in mii mode. rmiimiis g19 i rmii or mii selection: set high to configure the mac for rmii interfacing. set low for mii interfacing.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 29 of 338 name pin type description phy management bus mdc c19 o management data clock (mii): clocks management data between the phy and DS33R11. the clock is derived from the ref_clk, with a maximum frequency is 1.67mhz. the user must leave this pin unconnected in the dce mode. mdio c20 io mii management data io (mii): data path for control information between the phy and DS33R11. when not used, pull to logic high externally through a 10k resistor. the mdc and mdio pins are used to write or read up to 32 control and status registers in 32 phy controllers. this port can also be used to initiate auto- negotiation for the phy. the user must leave this pin unconnected in the dce mode. sdram interface scas w7 o sdram column address strobe: active-low output, used to latch the column address on the rising edge of sdclko. it is used with commands for bank activate, precharge, and mode register write. sras w9 o sdram row address strobe: active-low output, used to latch the row address on rising edge of sdclko. it is used with commands for bank activate, precharge, and mode register write. sdcs v10 o sdram chip select: active-low output enables sdram access. swe w10 o sdram write enable: this active-low output enables write operation and auto precharge. sba[0] y11 sba[1] v11 o sdram bank select: these 2 bits select 1 of 4 banks for the read/write/precharge operations. note: all sdram operations are controlled entirely by the DS33R11. no user programming for sdram buffering is required.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 30 of 338 name pin type description sdata[0] w2 sdata[1] y4 sdata[2] y2 sdata[3] y5 sdata[4] y3 sdata[5] w5 sdata[6] v5 sdata[7] w6 sdata[8] v6 sdata[9] w4 sdata[10] v4 sdata[11] v2 sdata[12] v3 sdata[13] v1 sdata[14] w3 sdata[15] w1 sdata[16] y16 sdata[17] y17 sdata[18] v18 sdata[19] y19 sdata[20] v19 sdata[21] y20 sdata[22] u19 sdata[23] w20 sdata[24] u20 sdata[25] t19 sdata[26] t20 sdata[27] y18 sdata[28] w19 sdata[29] v17 sdata[30] w17 sdata[31] w16 o sdram data bus bits 0 to 31: the 32 pins of the sdram data bus are inputs for read operations and outputs for write operations. at all other times, these pins are high-impedance. note: all sdram operations are controlled entirely by the DS33R11. no user programming for sdram buffering is required. sda[0] w14 sda[1] w12 sda[2] y15 sda[3] w15 sda[4] y14 sda[5] v13 sda[6] w13 sda[7] y12 sda[8] v12 sda[9] y10 sda[10] v14 sda[11] w11 o sdram address bus 0 to 11: the 12 pins of the sdram address bus output the row address first, followed by the column address. the row address is determined by sda0 to sda11 at the rising edge of clock. column address is determined by sda0-sda9 and sda11 at the rising edge of the clock. sda10 is used as an auto- precharge signal. note: all sdram operations are controlled entirely by the DS33R11. no user programming for sdram buffering is required. sdmask[0] y6 sdmask[1] v7 sdmask[2] v16 sdmask[3] v15 o sdram mask 0 through 3: when high, a write is done for that byte. the least significant byte is sdata7 to sdata0. the most significant byte is sdata31 to sdata24.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 31 of 338 name pin type description sdclko y8 o (4ma) sdram clk out: system clock output to the sdram. this clock is a buffered version of sysclki. t1/e1/j1 analog line interface ttip r1, r2 o transmit analog tip output for the t1/e1/j1 transceiver: analog line-driver outputs. tw o connections are provided to improve signal quality. these pins connect via a 1:2 step-up transformer to the network. see section 10.25 for details. tring t1,t2 o transmit analog ring output for the t1/e1/j1 transceiver: analog line-driver outputs. tw o connections are provided to improve signal quality. these pins connect via a 1:2 step-up transformer to the network. see section 10.25 for details. rtip k1 i receive analog tip input for the t1/e1/j1 transceiver: analog input for clock recovery circuitry. these pins connect via a 1:1 transformer to the network. see section 10.25 for details rring m1 i receive analog ring input for the t1/e1/j1 transceiver: analog input for clock recovery circuitry. these pins connect via a 1:1 transformer to the network. see section 10.25 for details t1/e1/j1 transmit framer interface tseri e3 i transmit serial data input to the t1/e1/j1 framer: transmit nrz serial data. sampled on the falling edge of tclkt when the transmit-side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit-side elastic store is enabled. tclkt d2 i transmit clock for the t1/e1/j1 transceiver: 1.544mhz or a 2.048mhz primary clock. used to clock data from the tseri pin through the transmit-side formatter. tchblk a2 o transmit channel block for the t1/e1/j1 transceiver: a user- programmable output that can be forced high or low during any of the channels. synchronous with tclkt when the transmit-side elastic store is disabled. synchronous with tsysclk when the transmit-side elastic store is enabled. useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. tchclk g1 o transmit channel clock for the t1/e1/j1 transceiver: a 192khz (t1) or 256khz (e1) clock that pulses high during the lsb of each channel. can also be programmed to output a gated transmit-bit clock for fractional t1/e1 applications. synchronous with tclkt when the transmit-side elastic store is disabled. synchronous with tsysclk when the transmit-side elastic store is enabled. useful for parallel-to-serial conversion of channel data. tssync a5 i transmit system sync for the t1/e1/j1 transceiver: only used when the transmit-side elastic store is enabled. a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. should be tied low in applications that do not use the transmit- side elastic store. tsync c1 i/o transmit sync for the t1/e1/j1 transceiver: a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. can be programmed to output either a frame or multiframe pulse. if this pin is set to output pulses at frame boundaries, it can also be set via tr.iocr1.3 to output double-wide pulses at signaling frames in t1 mode.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 32 of 338 name pin type description tsysclk e4 i transmit system clock for the t1/e1/j1 transceiver: 1.544mhz, 2.048mhz, 4.096mhz, 8.192mhz, or 16.384mhz clock. only used when the transmit-side elastic-store function is enabled. should be tied low in applications that do not use the transmit-side elastic store. tsig b4 i transmit signaling input fo r the t1/e1/j1 transceiver: when enabled, this input will sample signaling bits for insertion into outgoing pcm data stream. sampled on the falling edge of tclkt when the transmit-side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit-side elastic store is enabled. ethernet mapper transmit serial interface tsero e2 o transmit serial data output from ethernet mapper: output on the rising edge of tclke. selective clock periods can be skipped for output of tsero with a gapped clock input on tclke. the maximum data rate is 52mbit/s. tclke f1 i serial interface transmit clo ck input to ethernet mapper: the clock reference for tsero, which is output on the rising edge of the clock. tclke supports gapped clocking, up to a maximum frequency of 52mhz. tden/ tbsync d5 io transmit data enable (input): the transmit data enable is programmable to selectively block/enable the transmit data. the tden signal must occur one clock edge prior to the affected data bit. the active polarity of tden is programmable in register li.tslcr. it is recommended for both t1/e1 and t3/e3 applications that use gapped clocks. the tden signal is provided for interfacing to framers that do not have a gapped clock facility. transmit byte sync (output): this output can be used by an external serial to parallel to convert tsero stream to byte wide data. this output indicates the last bit of the byte data sent serially on tsero. this signal is only active in the x.86 mode. t1/e1/j1 receive framer interface rsero h2 o receive serial data for t1/e1/j1 transceiver: received nrz serial data. updated on rising edges of rclko when the receive- side elastic store is disabled. updated on the rising edges of rsysclk when the receive-side elastic store is enabled. rclko g3 o receive clock output from the t1/e1/j1 framer: 1.544mhz (t1) or 2.048mhz (e1) clock that is used to clock data through the receive-side framer. normally connected to the rclki input. rchblk a1 o receive channel block for the t1/e1/j1 transceiver: a user- programmable output that can be forced high or low during any of the 24 t1 or 32 e1 channels. synchronous with rclko when the receive-side elastic store is disabled. synchronous with rsysclk when the receive-side elastic store is enabled. also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. see the channel blocking registers section.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 33 of 338 name pin type description rchclk g2 o receive channel clock for the t1/e1/j1 transceiver: a 192khz (t1) or 256khz (e1) clock that pulses high during the lsb of each channel can also be programmed to output a gated receive-bit clock for fractional t1/e1 applications. synchronous with rclko when the receive-side elastic store is disabled. synchronous with rsysclk when the receive-side elastic store is enabled. useful for parallel-to-serial conversion of channel data. rsync g4 i/o receive sync for the t1/e1/j1 transceiver: an extracted pulse, one rclko wide, is output at this pin, which identifies either frame (tr.iocr1.5 = 0) or multiframe (tr.iocr1.5 = 1) boundaries. if set to output-frame boundaries then via tr.iocr1.6, rsync can also be set to output double-wide pulses on signaling frames in t1 mode. if the receive-side elastic store is enabled, then this pin can be enabled to be an input via tr.iocr1.4 at which a frame or multiframe boundary pulse is applied. rsysclk f4 i receive system clock for the transceiver: 1.544mhz, 2.048mhz, 4.096mhz, or 8.192mhz clock. only used when the receive-side elastic-store functi on is enabled. should be tied low in applications that do not use the receive-side elastic store. rfsync a3 o receive frame sync (pre receive elastic store) for t1/e1/j1 transceiver: an extracted 8khz pulse, one rclko wide, is output at this pin, which identifies frame boundaries. rmsync u3 o receive multiframe sync for the t1/e1/j1 transceiver: an extracted pulse, one rclko wide (elastic store disabled) or one rsysclk wide (elastic store enabled), is output at this pin, which identifies multiframe boundaries. rsig l3 o receive signaling output: outputs signaling bits in a pcm format. updated on rising edges of rclko when the receive-side elastic store is disabled. updated on the rising edges of rsysclk when the receive-side elastic store is enabled.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 34 of 338 name pin type description ethernet mapper receive serial interface rseri h1 i receive serial data input to ethernet mapper: receive serial data arrives on the rising edge of rclki. normally connected to rsero. rclki f2 i serial interface receive clock i nput to the ethernet mapper: reference clock for receive serial data on rseri. gapped clocking is supported, up to the maximum rclki frequency of 52 mhz. rden/ rbsync p2 i receive data enable for the ethernet mapper: the receive data enable is programmable to block the receive data. the rden must be coincident with the rseri data bit to be blocked or enabled. the active polarity of rden is programmable in register li.rslcr . it is recommended for both t1/e1 and t3/e3 applications that use gapped clocks. the rden signal is provided for interfacing to framers that do not have a gapped clock facility. receive byte sync hronization input: provides byte synchronization input to x.86 decoder. this signal will go high at the last bit of the byte as it arrives. this signal can occur at maximum rate every 8 bits. note that a long as the r11 receives one rbsync indicator. the x.86 receiver will determine the byte boundary. hence the r11 does not require a continuous 8 bit sync indicator. a new sync pulse is required if the byte boundary changes. t1/e1/j1 framer/liu interim signals rdclki m4 i receive clock input to the t1/e1/j1 framer: clock used to clock data through the receive-side framer. this pin is normally connected to rdclko. can be internally connected to rdclko by connecting the liuc pin high. rdclko m3 o receive clock output from the t1/e1/j1 liu: buffered recovered clock from the network. this pin is normally connected to rdclki. rnegi l4 i receive negative-data input: sampled on the falling edge of rdclki for data to be clocked through the receive-side framer. rposi and rnegi can be connected together for an nrz interface. can be internally connected to rnego by connecting the liuc pin high. rnego n2 o receive negative data output from the t1/e1/j1 liu: updated on the rising edge of rdclko with the bipolar data out of the line interface. this pin is normally tied to rnegi. rposi j3 i receive positive-data input to the t1/e1/j1 framer: sampled on the falling edge of rdclki for data to be clocked through the receive-side framer. rposi and rnegi can be connected together for an nrz interface. can be internally connected to rposo by connecting the liuc pin high. rposo n3 o receive positive-data output from the t1/e1/j1 liu: updated on the rising edge of rdclko with bipolar data out of the line interface. this pin is normally connected to rposi. rdata h3 o receive data from the t1/e1/j1 framer: updated on the rising edge of rclko with the data out of the receive-side framer, before passing through the elastic store. tdclki d1 i serial interface transmit clo ck input for the t1/e1/j1 liu: line interface transmit clock. this pin is normally tied to tclko. can be internally connected to tclko by connecting the liuc pin high.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 35 of 338 name pin type description tdclko c2 o transmit clock output from the t1/e1/j1 framer: buffered clock that is used to clock data through the transmit-side formatter (either tclkt or rdclki). this pin is normally tied to tdclki. tnegi c3 i transmit negative-data input: sampled on the falling edge of tdclki for data to be transmitted out onto the t1 line. can be internally connected to tnego by connecting the liuc pin high. tposi and tnegi can be connected together in nrz applications. tnego d3 o transmit negative-data output: updated on the rising edge of tclko with the bipolar data out of the transmit-side formatter. this pin is normally connected to tnegi. tposi b3 i transmit positive-data input: sampled on the falling edge of tdclki for data to be transmitted out onto the t1 line. can be internally connected to tposo by connecting the liuc pin high. tposi and tnegi can be connected together in nrz applications. tposo e1 o transmit positive-data output: updated on the rising edge of tclko with the bipolar data out of the transmit-side formatter. can be programmed to source nrz data by the output data format (tr.iocr1.0) control bit. this pin is normally connected to tposi. tdata a4 i transmit data: sampled on the falling edge of tclkt with data to be clocked through the transmit-side formatter. this pin is normally connected to teso. teso d4 o transmit elastic store output: updated on the rising edge of tclkt with data out of the transmit-side elastic store whether the elastic store is enabled or not. this pin is normally connected to tdata.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 36 of 338 name pin type description hardware and status pins liuc b2 i line interface unit connect: when a logic low is present on this input pin, the t1/e1/j1 framer and liu are not internally connected. the line interface circuitry will be separated from the framer/formatter circuitry and the tposi, tnegi, tdclki, rposi, rnegi, and rdclki input pins will be active. when a logic high is present on this input pin, the t1/e1/j1 framer is internally connected to the liu. the tposi, tnegi, tdclki, rposi, rnegi, rdclki input pins are deactivated. when liuc is connected high, the tposi, tnegi, tdclki, rposi, rnegi, and rdclki pins should be tied low. rst a8 i reset for the ethernet mapper: an active low signal on this pin resets the internal registers and logic of the protocol conversion device. this pin should remain low until power, sysclki, rx_clk, and tx_clk are stable, then set high for normal operation. this input requires a clean edge with a rise time of 25ns or less to properly reset the device. tstrst c4 i test/reset for the t1/e1/j1 transceiver: a dual-function pin. a zero-to-one transition issues a hardware reset to the transceiver register set. a reset clears all configuration registers. configuration register contents are set to zero. leaving tstrst high will tri-state all output and i/o pins (including the parallel control port). set low for normal operation. useful in board-level testing. modec[0], modec[1] b19, b20 i mode control for processor interface: 00 = read/write strobe used (intel mode) 01 = data strobe used (motorola mode) 10 = reserved. do not use. 11 = reserved. do not use. qovf h18 o queue overflow for ethernet mapper: this pin goes high when the transmit or receive queue has overflowed. this pin will go low when the high watermark is reached again. rlos/ltc n1 o t1/e1/j1 receive loss-of-sync/loss-of-transmit clock: a dual function output that is controlled by the ccr1.0 control bit. this pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the tclkt pin has not been toggled for 5  s. rcl b5 o t1/e1/j1 receive carrier loss: set high when the t1/e1/j1 line interface detects a carrier loss. rsigf p3 o t1/e1/j1 receive signaling-freeze output: set high when the signaling data is frozen by either automatic or manual intervention. used to alert downstream equipment of the condition.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 37 of 338 name pin type description system clocks sysclki v8 i system clock in for ethernet mapper: 100mhz system clock input to the DS33R11, used for internal operation. this clock is buffered and provided at sdclko for the sdram interface. the DS33R11 also provides a divided ve rsion output at the ref_clko pin. a clock supply with 100ppm frequency accuracy is suggested. mclk h4 i master clock input for the t1/e1/j1 transceiver: a (50ppm) clock source. this clock is used internally for both clock/data recovery and for the jitter attenuator for both t1 and e1 modes. the clock rate can be 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz. when using the transceiver in t1-only operation a 1.544mhz (50ppm) clock source can be used. bpclk b1 o backplane clock from t1/e1/j1 transceiver: a user-selectable synthesized clock output that is referenced to the clock that is output at the rclko pin. 8xclk k4 o eight times clock from the t1/e1/j1 transceiver: an 8x clock that is locked to the recovered network clock provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from the tdclki pin (if the jitter attenuator is enabled on the transmit side). xtald j4 o quartz crystal driver for the t1/e1/j1 transceiver: a quartz crystal of 2.048mhz (optional 1.544mhz in t1-only operation) can be applied across mclk and xtald instead of a clock source at mclk. leave open circuited if a clock source is applied at mclk.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 38 of 338 name pin type description jtag interface jtclk1 a7 ipu jtag clock 1 for the ethernet mapper: this signal is used to shift data into jtdi1 on the rising edge and out of jtdo1 on the falling edge. jtdi1 c9 ipu jtag data in 1 for the ethernet mapper: test instructions and data are clocked into this pin on the rising edge of jtclk1. this pin has a 10k  pullup resistor. jtdo1 b7 oz jtag data out 1 for the ethernet mapper: test instructions and data are clocked out of this pin on the falling edge of jtclk1. if not used, this pin should be left unconnected. jtms1 c8 ipu jtag mode select 1 for the ethernet mapper: this pin is sampled on the rising edge of jtclk1 and is used to place the test access port into the various defined ieee 1149.1 states. this pin has a 10k  pullup resistor. jtrst1 c7 ipu jtag reset 1 for the ethernet mapper: jtrst1 is used to asynchronously reset the test access port controller. after power up, a rising edge on jtrst1 will reset the test port and cause the device i/o to enter the jtag device id mode. pulling jtrst1 low restores normal device operation. jtrst1 is pulled high internally via a 10k  resistor operation. if boundary scan is not used, this pin should be held low. jtclk2 a6 ipu jtag clock 2 for the t1/e1/j1 transceiver: this signal is used to shift data into jtdi1 on the rising edge and out of jtdo1 on the falling edge. jtdi2 b6 ipu jtag data in 2 for the t1/e1/j1 transceiver: test instructions and data are clocked into this pin on the rising edge of jtclk2. this pin has a 10k  pullup resistor. jtdo2 c5 oz jtag data out 2 for the t1/e1/j1 transceiver: test instructions and data are clocked out of this pin on the falling edge of jtclk2. if not used, this pin should be left unconnected. jtms2 b9 ipu jtag mode select 2 for the t1/e1/j1 transceiver: this pin is sampled on the rising edge of jtclk2 and is used to place the test- access port into the various defined ieee 1149.1 states. this pin has a 10k  pullup resistor. jtrst2 b8 ipu jtag reset 2 for the t1/e1/j1 transceiver: jtrst2 is used to asynchronously reset the test access port controller. after power- up, jtrst2 must be toggled from low to high. this action will set the device into the jtag device id mode. normal device operation is restored by pulling jtrst2 low. jtrst2 is pulled high internally via a 10k  resistor operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 39 of 338 name pin type description power supplies rvdd k3, l1 ? receive analog positive supply: connect to 3.3v power supply. rvss j1, j2, k2, l2, m2 ? receive analog signal ground: connect to the common supply ground. tvdd u1 ? transmit analog positive supply: connect to 3.3v power supply. tvss p1, r3, t3, u2 ? transmit analog signal ground: connect to the common supply ground. dvdd d1?d17, e17 ? digital positive supply: connect to 3.3v power supply. dvss n4, p4, r4, t4 ? digital signal ground: connect to the common supply ground. vdd1.8 b10, b15, c12, f3, j18, j20, p18, p19, r19, r20, v9, y9, y13 i vdd1.8: connect to 1.8v power supply. vdd3 d20, f17, g17, g18, h17, j17, k17, l17, m17, n17, p17, r17, r18, t17, t18, u17 i vdd3.3: connect to 3.3v power supply. vss a15, c10, d8, d9, d10, d18, d19, e18, h20, j19, k20, n19, n20, p20, u4?u16, u18, v20, w8, w18, y1, y7 i vss: connect to the common supply ground. n.c. a9, c6, d6 ? no connection. do not connect these pins. leave these pins open.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 40 of 338 figure 7-1. 256-ball bga pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a rchblk tchblk rfsync tdata tssync jtclk2 jtclk1 rst n.c. int cs d6 d3 d0 vss a6 a3 a0 ref_clk ref_ clko b bpclk liuc tposi tsig rcl jtdi2 jtdo1 jtrst2 jtms2 vdd1.8 rd/ds d7 d4 d1 vdd1.8 a7 a4 a1 modec [0] modec [1] c tsync tdclko tnegi tstrst jtdo2 n.c. jtrst1 jtms1 jtdi1 vss wr/ r w vdd1.8 d5 d2 a9 a8 a5 a2 mdc mdio d tdclki tclkt tnego teso tden/ tbsync n.c. cst vss vss vss dvdd dvdd dvdd dvdd dvdd dvdd dvdd vss vss vdd3 e tposo tsero tseri tsysclk dvdd vss txd [3] txd [2] f tclke rclki vdd1.8 rsysclk vdd3 txd [1] txd [0] tx_en g tchclk rchclk rclko rsync vdd3 vdd3 rmiimiis dce dtes h rseri rsero rdata mclk vdd3 qovf tx_clk vss j rvss rvss rposi xtald vdd3 vdd1.8 vss vdd1.8 k rtip rvss rvdd 8xclk vdd3 rx_err rx_dv vss l rvdd rvss rsig rnegi vdd3 rxd [0] rxd [1] rxd [2] m rring rvss rdclko rdclki vdd3 rxd [3] rx_crs / crs_dv rx_clk n rlos/ ltc rnego rposo dvss vdd3 col_det vss vss p tvss rden/ rbsync rsigf dvss vdd3 vdd1.8 vdd1.8 vss r ttip ttip tvss dvss vdd3 vdd3 vdd1.8 vdd1.8 t tring tring tvss dvss vdd3 vdd3 sdata [25] sdata [26] u tvdd tvss rmsync vss vss vss vss vss vss vss vss vss vss vss vss vss vdd3 vss sdata [22] sdata [24] v sdata [13] sdata [11] sdata [12] sdata [10] sdata [6] sdata [8] sdmask [1] sysclki vdd1.8 sdcs sba [1] sda [8] sda [5] sda [10] sdmask [3] sdmask [2] sdata [29] sdata [18] sdata [20] vss w sdata [15] sdata [0] sdata [14] sdata [9] sdata [5] sdata [7] scas vss sras swe sda [11] sda [1] sda [6] sda [0] sda [3] sdata [31] sdata [30] vss sdata [28] sdata [23] y vss sdata [2] sdata [4] sdata [1] sdata [3] sdmask [0] vss sdclko vdd1.8 sda [9] sba [0] sda [7] vdd1.8 sda [4] sda [2] sdata [16] sdata [17] sdata [27] sdata [19] sdata [21]
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 41 of 338 8 functional description the DS33R11 provides interconnection and mapping functi onality between ethernet packet lans and t1/e1/j1 wan time-division multiplexed (tdm) systems. the device is composed of a 10/100 ethernet mac, packet arbiter, committed information rate controller (cir), hdlc/x.86 (laps) mapper, sdram interface, control ports, bit error-rate tester (bert), and integrated t1/e1/j1 transceiver. the packet interf ace consists of a mii/rmii ethernet phy interface. the ethernet interface can be configured for 10mbit/s or 100mbit/s service. the DS33R11 encapsulates ethernet traffic with hdlc or x.86 (laps) encoding to be transmitted over a t1, e1, or j1 line. the t1/e1/j1 interface also receives encapsulated ethernet packets and transmits the extracted packets over the ethernet ports. access is provided to the signals between t he serial port and the integrated t1/e1/j1 transceiver. the ethernet packet interface supports mii and rmii interfaces, allowing the dsz33r11 to connect to commercially available ethernet phy and mac devices. the ethernet in terface can be configured for 10mbit/s or 100mbit/s service, in dte and dce configurations. the DS33R11 mac interface rejects frames with bad fcs and short frames (less than 64 bytes). ethernet frames are queued and stored in external 32- bit sdram. the DS33R11 sdram controller enables connection to a 128mb sdram without external glue logi c, at clock frequencies up to 100mhz. the sdram is used for both the transmit and receive data queues. the receive queue stores data to be sent from the packet interface to the wan serial interface. the transmit queue stores data to be sent from the wan serial interface to the ethernet lan packet interface. the external sdram can accommodate up to 8192 frames with a maximum frame size of 2016 bytes. the sizing of the queues can be adjusted by software. the user can also program high and low watermarks for each queue that can be used for automatic or manual flow control. the packet data stored in the sdram is encapsulated in hdlc or x.86 (laps) to be transmitted over the wan interface. the device also provides the capability for bit and packet scrambling. the wan interface also receives encapsulated ethernet packets and transmits the extracted packets over the ethernet port. the wan serial port can operate with a gapped clock, and is designed to be connected to the integrated t1/e1/j1 transceiver for transmission. the DS33R11 can be configured through an 8-bit microprocessor interface port. diagnostic capabilities include loopbacks, prbs pattern generation/detection, and 16-bi t loop-up/loop-down code generation and detection. the DS33R11 provides two on-board clock dividers for the syst em-clock input and reference-clock input for the 802.3 interfaces, further reducing the need for ancillary devices. the integrated transceiver is a software-selectable t1, e1, or j1 single-chip transceiver (sct) for short-haul and long-haul applications. the transceiver is composed of an liu, framer, hdlc controllers, and a tdm backplane interface, and is controlled by the 8-bit parallel port. the transceiver is software compatible with the ds2155 and ds2156. the liu is composed of transmit and receive interfaces and a jitter attenuator. the transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. t1 waveform generation includes dsx-1 line build-outs as well as csu line build-outs of -7.5db, -15db, and -22.5db. e1 waveform generation includes g.703 waveshapes for both 75  coax and 120  twisted cables. the receive interface provides network termination and recovers clock and data from the network. the receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43db or 0 to 12db for e1 applications and 0 to 30db or 0 to 36db for t1 applications. the jitter attenuator removes phase jitter from the transmitted or received signal. the crystal-less jitter attenuator requires only a 2.048mhz mclk for both e1 and t1 applications (with the option of using a 1.544mhz mclk in t1 applications) and can be placed in either transmit or receive data paths. an additional featur e of the liu is a cmi coder/decoder for interfacing to optical networks. on the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. the framer inserts the appropriate synchronizati on framing patterns, alarm information, calculates and inserts the crc codes, and provides the b8zs/hdb3 (zer o code suppression) and ami line coding. the receive- side framer decodes ami, b8zs, and hdb3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/crc errors, and provides clock/dat a and frame-sync signals to the backplane interface section. both the transmit and receive path of the integrated t1/e1/j1 transceiver also have two hdlc controllers. the hdlc controllers transmit and receive data through the framer block. the hdlc controllers can be assigned to any
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 42 of 338 time slot, group of time slots, portion of a time slot or to fdl (t1) or sa bits (e1). each controller has 128-byte fifos, thus reducing the amount of processor overhead required to manage the flow of data. in addition, built-in support for reducing the processor time is required in ss7 applications. the backplane interface provides a versatile method of sending and receiving data from the host system. elastic stores provide a method for interfacing to asynchronous systems, converting from a t1/e1 network to a 2.048mhz, 4.096mhz, 8.192mhz, or n x 64khz system backplane. the elastic stores also manage slip conditions (asynchronous interface). 8.1 processor interface microprocessor control of the DS33R11 is accomplished through the interface pins of the microprocessor port. the 8-bit parallel data bus can be configured for intel or motorola modes of operation with the two modec[1:0] pins. when modec[1:0] = 00, bus timing is in intel mode, as shown in figure 13-9 and figure 13-10 . when modec[1:0] = 01, bus timing is in motorola mode, as shown in figure 13-11 and figure 13-12 . the address space is mapped through the use of 10 address lines, a0-a9. multiplexed mode is not supported on the processor interface. see the timing diagrams in ac electrical characteristics in section 13 for more details. the chip select ( cs ) pin must be brought to a logic low level to gain read and write access to the microprocessor port. with intel timing selected, the read ( rd ) and write ( wr ) pins are used to indicate read and write operations and latch data through the interface. with motorola timing selected, the read-write (r w ) pin is used to indicate read and write operations while the data strobe ( ds ) pin is used to latch data through the interface. the interrupt output pin ( int ) is an open-drain output that will assert a logic-low level upon a number of software maskable interrupt conditions. this pin is normally connected to the microprocessor interrupt input. the register map is shown in table 11-1 . 8.1.1 read-write/data strobe modes the processor interface can operate in either read-write strobe mode or data strobe mode. when modec[1:0] = 00 the read-write strobe mode is enabled and a negative pulse on rd performs a read cycle, and a negative pulse on wr performs a write cycle. when modec[1:0] pins = 01 the data strobe mode is enabled and a negative pulse on ds when r w is high performs a read cycle, and a negative pulse on ds when r w is low performs a write cycle. the read-write strobe mode is commonly called the ?intel? mode, and the data strobe mode is commonly called the ?motorola? mode. 8.1.2 clear on read the latched status registers will clear on a read access. it is important to note that in a multi-task software environment, the user should handle all status conditions of eac h register at the same time to avoid inadvertently clearing status conditions. the latched status register bits are carefully designed so that an event occurrence cannot collide with a user read access. 8.1.3 interrupt and pin modes the interrupt ( int ) pin is configurable to drive high or float w hen not active. the intm bit controls the pin configuration, when it is set the int pin will drive high when not active. after reset, the int pin is in high-impedance mode until an interrupt source is active and enabled to drive the interrupt pin.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 43 of 338 9 ethernet mapper 9.1 ethernet mapper clocks the DS33R11 clocks sources and functions are as follows:  serial transmit data (tclke) and serial receive data (rclki) clock inputs are used to transfer data from the serial interface. these clocks can be continuous or gapped.  system clock (sysclki) input. used for internal operation. this clock input cannot be a gapped clock. a clock supply with 100ppm frequency accuracy is suggested. a buffered version of this clock is provided on the sdclko pin for the operation of the sdram. a di vided and buffered version of this clock is provided on ref_clko for the rmii/mii interface.  packet interface reference clock (ref_clk) input that can be 25mhz or 50mhz. this clock is used as the timing reference for the rmii/mii interface. the user can utilize the built-in ref_clko output clock to drive this input.  the transmit and receive clocks for the mii interface (tx_clk and rx_clk). in dte mode, these are input pins and accept clocks provided by an ethernet phy. in the dce mode, these are output pins and will output an internally generated clock to the ethernet phy. the output clocks are generated by internal division of ref_clk. in rmii mode, only the ref_clk input is used.  ref_clko is an output clock that is generated by dividing the 100mhz system clock (sysclki) by 2 or 4. this output clock can be used as an input to ref_clk, allowing the user to have one less oscillator for the system.  a management data clock (mdc) output is derived from sysclki and is used for information transfer between the internal ethernet mac and external phy. the mdc clock frequency is 1.67mhz. clocking of the integrated t1/e1/j1 tansceiver is discussed in section 10.1 . the following table provides the different clocking options for the ethernet interface. table 9-1. clocking options for the ethernet interface rmiimiis pin speed dce/ dte ref_clko output ref_clk input rx_clk tx_clk mdc output 0 (mii) 10 mbps dte 25mhz 25mhz 100ppm input from phy input from phy 1.67mhz 0 (mii) 10 mbps dce 25mhz 25mhz 100ppm 2.5mhz (output) 2.5mhz (output) 1.67mhz 0 (mii) 100 mbps dce 25mhz 25mhz 100ppm 25mhz (output) 25mhz (output) 1.67mhz 1 (rmii) 10 mbps ? 50mhz 50mhz 100ppm not applicable not applicable 1.67mhz 1 (rmii) 100 mbps ? 50mhz 50mhz 100ppm not applicable not applicable 1.67mhz
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 44 of 338 figure 9-1. clocking for the DS33R11 ttip tring rtip rring sysclki ref_clko rx_clk ref_clk tx_clk mdc mclk xtald 8xclk bpclk tdclki tdclko tsysclk tchblk tchclk tclkt tclke tden jtclk2 rdclki rdclko rsyscl k rchbl k rchcl k rclko rclki rden transmit liu receive liu transmit framer receivie framer ethernet mac  p port sdram port sdcl k jtclk1 arbiter cir controller packet hdlc/x.86 packet hdlc/x.86 ethernet mapper t1/e1/j1 transceiver transmit serial port receive serial port jtag2 jtag1 clad mux mux clad bert bert hdlc hdlc note that the clocking options of the integrated t1/e1/j1 tansceiver are discussed in section 10.1.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 45 of 338 9.1.1 ethernet interface clock modes the ethernet phy interface has several different clocking requirements, depending on the mode of operation. the user has the option of using the internally generated ref_clko output to simplify the system design. table 9-1 outlines the possible clocking modes for the ethernet interface. the buffered ref_clko output is generated by division of the 100mhz system clock input by the user on sysclki. the frequency of the ref_clko pin is automatically determined by the DS33R11 based on the state of the rmiimiis pin. the ref_clko output can be used as a ref_clk for the ethernet interface by connecting ref_clko to ref_clk. the ref_clko function can be turned off with the gl.cr1 .rfoo bit. in rmii mode, receive and transmit timing is always synchronous to a 50 mhz clock input on the ref_clk pin. the source of ref_clk is expected to be the external phy. the user has the option of using the 50mhz ref_clko output as the timing source for the phy. more information on rmii mode can be found in section 9.15.2 . while using mii mode with dte operation, the mii clocks (rx_clk and tx_clk) are inputs that are expected to be provided by the external phy. while using mii mode wi th dce operation, the mii clocks (tx_clk and rx_clk) are output by the DS33R11, and are derived from the 25mhz ref_clk input. any 25mhz reference may be used, but the user may choose to use the ref_clko output to avoid adding another system clock. more information on mii mode can be found in section 9.15.1 . 9.1.2 serial interface clock modes the serial interface timing is determined by the line clocks. both the transmit and receive clocks (tclke and rclki) are inputs, and can be gapped.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 46 of 338 9.2 resets and low power modes the external rst pin and the global reset bit in gl.cr1 create an internal global reset signal. the global reset signal resets the status and control registers on the chip (except the gl.cr1 . rst bit) to their default values and resets all the other flops to their reset values. the processor bus output signals are also placed in high-impedance mode when the rst pin is active (low). the global reset bit (gl.cr1 . rst) stays set after a one is written to it, but is reset to zero when the external rst pin is active or when a zero is written to it. allow 5ms after initiating a reset condition for the reset operation to complete. the serial interface reset bit in li.rstpd resets all the status and control registers on the serial interface to their default values, except for the li.rstpd . rst bit. the serial interface includes the hdlc encoder/decoder, x86 encoder and decoder and the corresponding serial port. the serial interface reset bit (li.rstpd . rst) stays set after a one is written to it, but is reset to zero when the gl obal reset signal is active or when a zero is written to it. table 9-2. reset functions reset function location comments hardware device reset rst pin transition from a logic 0 to a logic 1 resets the device. hardware jtag reset jtrst pin resets the jtag test port. global software reset gl.cr1 writing to this bit resets the device. serial interface reset li.rstpd writing to this bit resets the serial interface. queue pointer reset gl.c1qpr writing to this bit resets the queue pointers there are several features in the DS33R11 to reduce power consumption. the reset bit in the li.rstpd and register also place the serial interface in a low-power mode. additionally, the rst pin may be held low indefinitely to keep the entire device in a low-power mode. note that ex iting the low-power condition requires re-initialization and configuration. the t1/e1/j1 transceiver contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the transceiver. the user can issue a chip reset at any time. issuing a reset disrupts traffic flowing through the transceiver until the device is reprogrammed. the reset can be issued through hardware using the tstrst pin or through software using the sftrst function in the master mode register. the lirst (tr.lic2.6) should be toggled from 0 to 1 to reset the line interface circuitry. (it takes the transceiver about 40ms to recover from the lirst bit being toggled.) finally, after the tsysclk and rsysclk inputs are stable, the receive and transmit elastic stores should be reset (this step can be skipped if the elastic stores are disabled).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 47 of 338 9.3 initialization and configuration example device initialization sequence: step 1: apply 3.3v supplies, then apply 1.8v supplies. step 2: reset the integrated ethernet mapper by pulling the rst pin low or by using the software reset bits outlined in section 9.2 . clear all reset bits. allow 5ms for the reset recovery. step 3: reset the integrated t1/e1/j1 transceiver through hardware using the tstrst pin or through software using the sftrst function in the master mode register. step 4: the lirst (tr.lic2.6) should be toggled from 0 to 1 to reset the line interface circuitry. allow 40ms for the reset recovery. step 5: check the ethernet mapper device id in the gl.idrl and gl.idrh registers. step 6: check the t1/e1/j1 transceiver device id in the tr.idr register. step 7: configure the system clocks. allow the clock system to properly adjust. step 8: initialize the entire remainder of the register space with 00h (or otherwise if specifically noted in the register?s definition), including the reserved bits and reserved register locations. step 9: write ffffffffh to t he mac indirect addresses 010ch through 010fh. step 10: setup connection in the gl.con1 register. step 11: configure the serial port register space as needed. step 12: configure the ethernet port register space as needed. step 13: configure the ethernet mac indirect registers as needed. step 14: configure the t1/e1/j1 framer as needed. step 15: configure the t1/e1/j1 liu as needed. step 16: configure the external ethernet phy through the mdio interface. step 17: clear all counters and latched status bits. step 18: set the queue size in the arbiter and reset the queue pointers for the ethernet and serial interfaces. step 19: after the tsysclk and rsysclk inputs to the t1/e1/j1 transceiver are stable, the receive and transmit elastic stores should be reset (this step can be skipped if the elastic stores are disabled). step 20: enable interrupts as needed. step 21: begin handling interrupts and latched status events. 9.4 global resources in order to maintain software compatibility with the multiport devices in the product family, a set of global registers are located at 0f0h-0ffh. the global registers include global resets, global interrupt status, interrupt masking, clock configuration, and the device id registers. see the global register definitions in table 11-2 . 9.5 per-port resources multiport devices in this product family share a common set of global registers, bert, and arbiter. all other resources are per-port.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 48 of 338 9.6 device interrupts figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. when an interrupt occurs, the host can read the global latched status registers gl.lis , gl.sis , gl.bis , and gl.trqis to initially determine the source of the interrupt. the host can then read the li.tqctls , li.tppsrl , li.rppsrl , li.rx86s , su.qcrls , or bsrl registers to further identify the source of the interrupt(s). in order to maintain software compatibility with the multiport devices in the product family, the global interrupt status and interr upt enable registers have been preserved, but do not need to be used. if gl.trqis is determined to be the interrupt source, the host will then read the li.tppsrl and li.rppsrl registers for the cause of the interrupt. if gl.lis is determined to be the interrupt source, the host will then read the li.tqctls, li.tppsrl, li.rppsrl, and li.rx86s registers for the source of the interrupt. if gl.sis is the source, the host will then read the su.qcrls register for the source of the interrupt. if gl.bis is the source, the host will then read the bsrl register for the source of the interrupt. all global interrupt status register bits are real-time bits that will clear once the appropriate interrupt has been serviced and cleared, as long as no additional, enabled interrupt conditions are present in the associated status register. all latched status bits must be cleared by the host writing a ?1? to the bit location of the interr upt condition that has been serviced. in order for individual status conditions to transmit their status to the next level of interrupt logic, they must be enabled by placing a ?1? in the associated bit location of the correct interrupt enable register. the interrupt enable registers are li.tppsrie , li.rppsrie , li.rx86lsie , bsrie, su.qrie, gl.lie, gl.sie, gl.bie , and gl.trqie. latched status bits that have been enabled via interrupt enable registers are allow ed to pass their interrupt conditions to the global interrupt status registers. the interrupt enable regist ers allow individual latched status conditions to generate an interrupt, but when set to zero, they do not prevent the latched status bits from being set. therefore, when servicing interrupts, the user should and the latched status with the associated interrupt enable register in order to exclude bits for which the user wished to prevent interrupt service. this architecture allows the application host to periodically poll the latched status bits for noninterrupt condi tions, while using only one set of registers. note the bit- orders of su.qrie and su.qcrls are different. note that the inactive state of the interrupt output pin is configurable. the intm bit in gl.cr1 controls the inactive state of the interrupt pin, allowing selection of a pull-up resistor or active driver . the interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. the latched status bits for the interrupting entity must be read to clear the interrupt. also reading the latched status bit will reset all bits in that register. during a reset condition, interrupts cannot be generated. the interrupts from any source can be blocked at a global level by the plac ing a zero in the global interrupt enable registers ( gl.lie , gl.sie, gl.bie, and gl.trqie). reading the latched status bit for all interrupt generating events will clear the interrupt status bit and interrupt signal will be de-asserted. note that the integrated t1/e1/j1 transceiver also generates interrupts, as discussed in section 10.3 .
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 49 of 338 figure 9-2. device interrupt information flow diagram receive fcs errored packet 7 receive aborted packet 6 receive invalid packet detected 5 receive small packet detected 4 receive large packet detected 3 receive fcs errored packet count 2 receive aborted packet count 1 receive size violation packet count 0 li.rppsl li.rppsrie 7 6 5 4 3 2 1 transmit errored packet insertion finished 0 li.tppsrl li.tppsrie 7 6 5 4 sapi high is not equal to li.trx86sapih 3 sapi low is not equal to li.trx86sapil 2 control is not equal to li.trx8c 1 address is not equal to li.trx86a 0 li.rx86s li.rx86lsie 7 6 5 4 transmit queue fifo overflowed 3 transmit queue overflow 2 transmit queue for connection exceeded low threshold 1 transmit queue for connection exceeded high threshold 0 li.tqctls li.tqtie 7 6 5 4 receive queue fifo overflowed 3 receive queue overflow 2 receive queue for connection exceeded low threshold 1 receive queue for connection exceeded high threshold 0 su.qcrls su.qrie 7 6 5 4 performance monitor update 3 bit error detected 2 bit error count 1 out of synchronization 0 bsrl bsrie drawing legend: interrupt status registers register name interrupt enable registers register name interrupt pin 7 6 5 4 3 2 1 0 gl.trqis gl.trqie 7 6 5 4 3 2 1 0 gl.lis gl.lie 7 6 5 4 3 2 1 0 gl.sis gl.sie 7 6 5 4 3 2 1 0 gl.bis gl.bie interrupts from t1/e1/j1 transceiver
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 50 of 338 9.7 interrupt information registers the interrupt information registers pr ovide an indication of which status r egisters (sr1 through sr9) are generating an interrupt. when an interrupt occurs, the host can read tr.iir1 and tr.iir2 to quickly identify which of the nine status registers are causing the interrupt. 9.8 status registers when a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit in a status register is set to a 1. all of the status registers operate in a latched fashion. this means that if an event or condition occurs a bit is set to a 1. it remains set until the user reads that bit. an event bit is cleared when it is read and it is not set again until the event has occurred again. condition bits such as rbl, rlos, etc., remain set if the alarm is still present. the user always proceeds a read of any of the status registers with a write. the byte written to the register informs the device which bits the user wishes to read and have cleared. the user writes a byte to one of these registers, with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user does not wish to obtain the latest information on. when a 1 is written to a bit location, the read register is updated with the latest information. when a 0 is written to a bit position, the read register is not updated and the previous value is held. a write to the status registers is immediately followed by a read of the same register. this write-read scheme allows an external microcontroller or microprocessor to individually poll certain bi ts without disturbing the other bits in the register. this operation is key in controlling the device with higher order languages. status register bits are divided into two groups, condition bits and event bits. condition bits are typically network conditions such as loss-of-sync or all-ones detect. event bits are typically markers such as the one-second timer, elastic store slip, etc. each status register bit is label ed as a condition or event bit. some of the status registers have bits for both the detection of a condition and the clear ance of the condition. for example, tr.sr2 has a bit that is set when the device goes into a loss-of-sync state (t r.sr2.0, a condition bit) and a bit that is set (tr.sr2.4, an event bit) when the loss-of-sync condition clears (goes in sy nc). some of the status register bits (condition bits) do not have a separate bit for the ?condition clear? event but rather the status bit can produce interrupts on both edges, setting and clearing. these bits are marked as double interrupt bits. an interrupt is produced when the condition occurs and when it clears. 9.9 information registers information registers operate the same as status registers except they cannot cause interrupts. they are all latched except for tr.info7 and some of the bits in tr.info5 and tr.info6. tr.info7 register is a read-only register. it reports the status of the e1 synchronizer in real time. tr.info7 and some of the bits in tr.info6 and tr.info5 are not latched and it is not necessary to precede a read of these bits with a write. 9.10 serial interface the serial (wan) interface is intended to be connected to the integrated t1/e1/j1 transceiver. however, the interface supports time-division multiplexed, serial dat a input and output up to 52 mbit/s. the serial interface receives and transmits encapsulated ethernet packets. the serial interface block consists of the physical serial port and hdlc / x.86 engine. the physical interface consists of a transmit data, transmit clock, transmit enable, receive data, receive clock, and receive enable. the wan serial port can operate with a gapped clock, and can be connected to a framer, electrical liu, optical transceiver, or t/e-carrier transceiver for transmission to the wan.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 51 of 338 9.11 connections and queues the multi-port devices in this product family provide bi directional cross-connections between the multiple ethernet ports and serial ports when operating in software mode. a single connection is preserved in this single-port device to provide software compatibility with multi-port devices. the connection will have an associated transmit and receive queue. note that the terms ?transmit queue? and ?receive queue? are with respect to the ethernet interface. the receive queue is for data arriving from ethernet interface to be transmitted to the wan interface. the transmit queue is for data arriving from the wan to be transmitted to the ethernet interface. hence the transmit and receive direction terminology is the same as is used for the ethernet mac port. the user can define the connection and the size of the transmit and receive queues. the size is adjustable in units of 32 (by 2048 byte) packets. the external sdram can hold up to 8192 packets of data. the user must ensure that all the connection queues do no exceed this limit. the user also must ensure that the transmit and receive queues do not overlap each other. unidirectional connections are not supported. when the user changes the queue sizes, the connection must be torn down and re-established. when a connection is disconnected all transmit and receive queues associated with the connection are flushed and a ?1? is sourced towards the serial transmit and the hdlc receiver. the clocks to the hdlc are sourced a ?0?. the user can also program high and low watermarks. if the queue size grows past the high watermark, an interrupt is generated if enabled. the registers of relevance are described in table 9-3 . the ar.tqsc1 size provides the size of the transmit queue for the connection. the high watermark will set a latched status bit. the latched status bit will clear when the register is read. the status bit is indicated by li.tqctls .tqhts. interrupts can be enabled on the latched bit events by li.tqtie . a latched status bit (li.tqctls.tqlts) is also set when the queue crosses a low watermark. the receive queue functions in a similar manner. note that the user must ensure that sizes and watermarks are set in accordance with the configuration speed of the ethernet and serial interfaces. the DS33R11 does not provide error indication if the user creates a c onnection and queue that overwrites data for another connection queue. the user must take care in setting the queue sizes and watermarks. the registers of relevance are ar.rqsc1 and su.qcrls . queue size should never be set to 0.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 52 of 338 it is recommended that the user reset the queue pointers for the connection after disconnection. the pointers must be reset before a connection is made. if this disconnect/connect procedure is not followed, incorrect data may be transmitted. the proper procedure for setting up a connection follows:  set up the queue sizes for both transmit and receive queue ( ar.tqsc1 and ar.rqsc1 ).  set up the high/low thresholds and interrupt enables if desired ( gl.trqie , li.tqtie , su.qrie ).  reset all the pointers for the connection desired ( gl.c1qpr ).  set up the connections ( gl.con1 ).  if a connection is disconnected, reset the queue pointers after the disconnection. table 9-3. registers related to connections and queues register function gl.con1 enables connection between the ethernet interface and the serial interface. note that once connection is set up, then the queues and thresholds can be setup for that connection. ar.tqsc1 size for the transmit queue in number of 32?2k packets. ar.rqsc1 size for the receive queue in number of 32?2k packets. gl.trqie interrupt enable for items related to the connections at the global level gl.trqis interrupt enable status for items related to the connections at the global level li.tqtie enables for the transmit queue crossing high and low thresholds li.tqctls latched status bits for connection high and low thresholds for the transmit queue. su.qrie enables for the receive queue crossing high and low thresholds su.qcrls latched status bits for receive queue high and low thresholds. gl.c1qpr resets the connection pointer. 9.12 arbiter the arbiter manages the transport between the ethernet port and the serial port. it is responsible for queuing and dequeuing packets to a single external sdram. the arbi ter handles requests from the hdlc and mac to transfer data to and from the sdram.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 53 of 338 9.13 flow control flow control may be required to ensure that data queues do not overflow and packets are not lost. the DS33R11 allows for optional flow control based on the queue high watermark or through host processor intervention. there are 2 basic mechanisms that are used for flow control:  in half duplex mode, a jam sequence is sent that causes collisions at the far end. the collisions cause the transmitting node to reduce the rate of transmission.  in full duplex mode, flow control is initiated by the receiving node sending a pause frame. the pause frame has a timer parameter that determines the pause timeout to be used by the transmitting node. note that the terms ?transmit queue? and ?receive queue? are with respect to the ethernet interface. the receive queue is the queue for the data that arrives on the mii/rmii interface, is processed by the mac and stored in the sdram. transmit queue is for data that arrives from the serial port, is processed by the hdlc and stored in the sdram to be sent to the mac transmitter. the following flow control options are possible:  automatic flow control can be enabled in software mode with the su.gcr .atflow bit. note that the user does not have control over su.macfcr .fce and fcb bits if atflow is set. the mechanism of sending pause or jam is dependent only on the receive queue high threshold.  manual flow control can be performed through software when su.gcr.atflow=0. the host processor must monitor the receive queues and generate pause frames (full duplex) and/or jam bytes through the su.macfcr.fcb, su.gcr.jame, and su.macfcr.fce bits. note that in order to use flow control, the receive queue size (in ar.rqsc1 ) must be 02h or greater. the receive queue high threshold (in su.rqht ) must be set to 01h or greater, but must be less than the queue size. if the high threshold is set to the same value as the queue size, automatic flow control will not be effective. the high threshold must always be set to less than the corresponding queue size. the following table provides all the options on flow control mechanism for DS33R11. table 9-4. options for flow control type mode configuration half duplex; manual flow control half duplex; automatic flow control full duplex; manual flow control full duplex; automatic flow control atflow bit 0 1 0 1 jame bit controlled by user controlled automatically n/a n/a fcb bit (pause) n/a n/a controlled by user controlled automatically fce bit controlled by user controlled automatically controlled by user controlled automatically pause timer n/a n/a programmed by user programmed by user
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 54 of 338 9.13.1 full duplex flow control automatic flow control is enabled by default. the host processor can disable this functionality with su.gcr .atflow. the flow control mechanism is governed by the high watermarks ( su.rqht ). the su.rqlt low threshold can be used as indication that the network congestion is clearing up. the value of su.rqlt does not affect the flow control. when the connection queue high threshold is exceeded the DS33R11 will send a pause frame with the timer value programmed by the user. see table 9-6 for more information. it is recommended that 80 slots (80 by 64 bytes or 5120 bytes) be used as the standard timer value. the pause frame causes the distant transmitter to ?pause for a time? before starting transmission again. the pause command has a multicast address 01-80-62-00-00-01. the high and low thresholds for the receive queue are configurable by the user but it is recommended that the high threshold be set approximately 96 packets from the maximum size of the queue and the low threshold 96 packets lower than the high threshold. the DS33R11 will send a pause frame as the queue has crossed the high threshold and a frame is received. pause is sent every time a frame is received in the ?high threshold state?. pause control will only take care of temporary congestion. pause control does not take care of systems where the traffic throughput is too high for the queue sizes selected. if the flow control is not effective the receive queue will eventually overflow. this is indicated by su.qcrls .rqovfl latched bit. if the receive queue is overflowed any new frames will not be received. the user has the option of not enabling automatic flow control. in this case the thresholds and corresponding interrupt mechanism to send pause frame by writing to flow control busy bit in the mac flow control registers su.macfcr .fcb, su.gcr.jame, and su.macfcr . this allows the user to set not only the watermarks but also to decide when to send a pause frame or not based on watermark crossings. on the receive side the user has control over whether to respond to the pause frame sent by the distant end (pcf bit). note that if automatic flow control is enabled the user cannot modify the fce bit in the mac flow control register. on the transmit queue the user has the option of setting high and low thresholds and corresponding interrupts. there is no automatic flow control mechanism for data received from the serial side waiting for transmission over the ethern et interface during times of heavy ethernet congestion.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 55 of 338 figure 9-3. flow control using pause control frame receive queue growth receive queue high water mark initiate flow control 8 rx data receive queue low water 9.13.2 half duplex flow control half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. the receiving node jams the first 4 bytes of a packet that are received from the mac in order to cause collisions at the distant end. in both 100mbit/s and 10mbit/s mii/rmii modes, 4 bytes are jammed upon reception of a new frame. note that the jamming mechanism does not jam the current frame that is being received during the watermark crossing, but will wait to jam the next frame after the su.rqht bit is set. if the queue remains above the high threshold, received frames will continue to be jammed. this jam sequence is stopped when the queue falls below the high threshold. 9.13.3 host-managed flow control although automatic flow control is recommended, flow control by the host processor is also possible. by utilizing the high watermark interrupts, the host processor can manually issue pause frames or jam incoming packets to exert backpressure on the transmitting node. pause frames can be initiated with su.macfcr.fcb bit. jam sequences can be initiated be setting su.gcr.jame. the host can detect pause frames by monitoring su.rfsb3.uf and su.rfsb3.cf. jammed frames will be indistinguishable from packet collisions.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 56 of 338 9.14 ethernet interface port the ethernet port interface allows for direct connection to an ethernet phy. the interface consists of a 10/100mbit/s mii/rmii interface and an ethernet mac. in rmii operation, the interface contains seven signals with a reference clock of 50 mhz. in mii operation, the interface contains 17 signals and a clock reference of 25mhz. the DS33R11 can be configured to rmii or mii interface by the hardware pin rmiimiis. the ref_clko output can be used to source the ref_clk input. if the port is configured for mii in dce mode, ref_clk must be 25mhz. the DS33R11 will internally generate the tx_clk and rx_clk outputs (at 25mhz for 100mbps, 2.5mhz for 10mbps) required for dce mode from the ref_clk input. in mii mode with dte operation, the tx_clk and rx_clk signals are generated by the phy and are inputs to the DS33R11. for more information on clocking the ethernet interface, see section 9.1 . the data received from the mii or rmii interface is processed by the internal ieee 802.3 complaint ethernet mac. the user can select the maximum frame size (up to 2016 bytes) that is received with the su.rmfsrh and su.rmfsrl registers. the maximum frame length (in bits) is the number specified in su.rmfsrh and su.rmfsrl multiplied by 8. any programmed value gr eater than 2016 bytes will result in unpredictable behavior and should be avoided. the maximum frame size is shown in figure 9-4 . the length includes only destination address, source address, vl an tag (2 bytes), type length field, data and crc32. the frame size is different than the 802.3 ?type length field.? frames from the ethernet phy or received from the packet processor are rejected if greater than the maximum frame size specified. each ethernet frame sent or received generates status bits ( su.tfsh and su.tfsl and su.rfsb0 to su.rfsb3 ). these are real-time status registers and will change as each frame is sent or received. hence they are useful to the user only when one frame is sent or received and the status is associated with the frame sent or received. figure 9-4. ieee 802.3 ethernet frame preamble sfd destination adrs source address type lenght data crc32 7 1 6 6 2 46-1500 4 max frame length encapsulated frame the distant end will normally reject the sent frames if jabber timeout, loss of carrier, excessive deferral, late collisions, excessive collisions, under run, deferred or collision errors occur. transmission of a frame under any of theses errors will generate a status bit in su.tfsl, su.tfsh. the DS33R11 provides user the option to automatically retransmit the frame if any of the errors have occurred through the bit settings in su.tfrc . deferred frames and heartbeat fail have separate resend control bits (su.tfrc.tfbfcb and su.tfrc.tprhbc). if there is no carrier (indicated by the mac transmit packet status), the transmit queue (data from the serial interface to the sdram to ethernet interface) can be selectively flushed. this is controlled by su.tfrc.ncfq.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 57 of 338 the mac circuitry generates a frame status for every frame that is received. this real time status can be read by su.rfsb0 to su.rfsb3 . note the frame status is the ?real time? status and hence the value will change as new frames are received. hence the real time status reflects the status in time and may not correspond to the current received frame being processed. this is also true for the transmitted frames. frames with errors are usually rejected by the DS33R11. the user has the option of accepting frames by settings in receive frame rejection control register ( su.rfrc ). the user can program whether to reject or accept frames with the following errors:  mii error asserted during the reception of the frame  dribbling bits occurred in the frame  crc error occurred  length error occurred?the length indicated by the frame length is inconsistent with the number of bytes received  control frame was received. the mode must be full duplex  unsupported control frame was received note that frames received that are runt frames or frames with collision will automatically be rejected. table 9-5. registers related to setting the ethernet port register function su.tfrc this register determines if the current frame is retransmitted due to various transmit errors. su.tfsl and su.tfsh these two registers provide the real-time status of the transmit frame. only apply to the last frame transmitted. su.rfsb0 to 3 these registers provide the real-time status for the received frame. only apply to the last frame received. su.rfrc this register provides settings for reception or rejection of frame based on errors detected by the mac. su.rmfsrh and su.rmfsrl the settings for this register provide the maximum size of frames to be accepted from the mii/rmii receive interface. su.maccr this register provides configuration control for the mac.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 58 of 338 9.14.1 dte and dce mode the ethernet mii/rmii port can be configured for dce or dte mode. when the port is configured for the dte mode it can be connected to an ethernet phy. in dce mode, the port can be connected to mii/rmii mac devices other than an ethernet phy. the dte/dce connections for the DS33R11 in mii mode are shown in the following two figures. in dce mode, the DS33R11 transmitter is connected to an external receiver and DS33R11 receiver is connected to an external mac transmitter. the selection of dte or dce mode is done by the hardware pin dcedtes. figure 9-5. configured as dte connected to an ethernet phy in mii mode mac rxd[3:0] rxd[3:0] rx_clk rx_clk rx_err rx_err rx_crs rx_crs col_det col_det ethernet phy tx_en tx_en mdc mdio txd[3:0] txd[3:0] tx_clk DS33R11 dce dte tx_clk mdio mdc rxdv rxdv rx rx tx tx
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 59 of 338 figure 9-6. DS33R11 configured as a dce in mii mode mac txd[3:0] rxd[3:0] tx_clk rx_clk tx_err rx_err tx_en rx_crs col_det col_det dte dce tx_en rxdv mdc mdio txd[3:0] rxd[3:0] tx_clk ds33z11 mac rx_clk rxdv rx_crs mdio mdc rx tx tx rx 9.15 ethernet mac indirect addressing is required to access the mac regist er settings. writing to the mac registers requires the su.macwd0 -3 registers to be written with 4 bytes of data. the address for the write operation must be written to su.macawl and su.macawh . a write command is issued by writing a zero to su.macrwc .mcrw and a one to su.macrwc.mcs (mac command status). mcs is cleared by the DS33R11 when the operation is complete. reading from the mac registers requires the su.macradh and su.macradl registers to be written with the address for the read operation. a read command is issued by writing a one to su.macrwc.mcrw and a zero to su.macrwc.mcs. su.macrwc.mcs is cleared by the ds 33r11 when the operation is complete. after mcs is clear, valid data is available in su.macrd0-su.macrd3. note that only one operation can be initiated (read or write) at one time. data cannot be written or read from the mac registers until the mcs bit has been cleared by the device. the mac registers are detailed in the following table.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 60 of 338 table 9-6. mac control registers address register description 0000h-0003h su.maccr mac control register. this register is used for programming full duplex, half duplex, promiscuous mode, and back-off limit for half duplex. the transmit and receive enable bits must be set for the mac to operate. 0014h-0017h su.macmiia mii address register. the address for phy access through the mdio interface. 0018h-001bh su.macmiid mii data register. data to be written to (or read from) the phy through mdio interface. 001ch-001fh su.macfcr flow control register 0100h-0103h su.mmcctrl mmc control register bit 0 for resetting the status counters table 9-7. mac status registers address register description 0200h-0203h su.rxfrmcntr all frames received counter 0204h-0207h su.rxfrmokctr number of received frames that are good 0300h-0303h su.txfrmctr number of frames transmitted 0308h-030bh su.txbytesctr number of bytes transmitted 030ch-030fh su.txbytesokctr number of bytes transmitted with good frames 0334h-0337h su.txfrmundr transmit fifo underflow counter 0338h-033bh su.txbdfrmsctr transmit number of frames aborted
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 61 of 338 9.15.1 mii mode options the ethernet interface can be configured for mii operation by setting the hardware pin rmiimiis low. the mii interface consists of 17 pins. for instructions on clocking the ethernet interface while in mii mode, see section 9.1 . diagrams of system connections for mii operation are shown in figure 9-5 and figure 9-6 . 9.15.2 rmii mode the ethernet interface can be configured for rmii operat ion by setting the hardware pin rmiimiis high. rmii interface operates synchronously from the external 50mhz reference (ref_clk). only seven signals are required. the following figure shows the rmii architecture. note that dce mode is not supported for rmii mode and rmii is valid only for full duplex operation. figure 9-7. rmii interface txd[1:0] tx_en ref_clk rxd[1:0] crs_dv DS33R11 mac external phy
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 62 of 338 9.15.3 phy mii management block and mdio interface the mii management block allows for the host to control up to 32 phys, each with 32 registers. the mii block communicates with the external phy using 2-wire serial interface composed of mdc (serial clock) and mdio for data. the mdio data is valid on the rising edge of the mdc clock. the frame format for the mii management interface is shown figure 9-8 . the read/write control of the mii management is accomplished through the indirect su.macmiia mii management address register and data is passed through the indirect su.macmiid data register. these indirect registers are access ed through the mac control registers defined in table 9-6 . the mdc clock is internally generated and runs at 1.67mhz. figure 9-8. mii management frame read 111...111 01 01 10 01 phya[4:0] phyr[4:0] zz 10 zzzzzzzzz z z preamble start opco de phy adrs phy reg turn aroun d data 111...111 phya[4:0] phyr[4:0] phyd[15:0] 32 bits 2 bits 2 bits 5 bits 5 bits 2 bits 16 bits idle 1 bit write 9.16 bert in the ethernet mapper the bert in the ethernet mapper can be used for generation and detection of bert patterns. the bert is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. the following restrictions are related to the bert:  the rden and tden are inputs that can be used to ?gap? bits.  bert will transmit even when the device is set for x.86 mode and tden is configured as an output.  the normal traffic flow is halted while the bert is in operation.  if the bert is enabled for a serial port, it will override the normal connection.  if there is a connection overridden by the bert, when bert operation is terminated the normal operation is restored. the transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data stream. the receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern payload for the programmable test pattern. bert features  prbs and qrss patterns of 2 9 -1, 2 15 -1 2 23 -1 and qrss pattern support.  programmable repetitive pattern. the repetitive pattern length and pattern are programmable. [length n = 1 to 32 and pattern = 0 to (2 n ? 1)].  24-bit error count and 32-bit bit count registers.  programmable bit error insertion. errors can be inserted individually.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 63 of 338 9.16.1 receive data interface 9.16.1.1 receive pattern detection the receive bert receives only the payload data and synchr onizes the receive pattern generator to the incoming pattern. the receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the i nput to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. qrss is programmable (on or off). for prbs and qrss patterns, the feedback is forced to one if bits 1 through 31 are all zeros. depending on the type of pattern programmed, pattern detection performs either prbs synchronization or repetitive pattern synchronization. 9.16.1.2 prbs synchronization prbs synchronization synchronizes the receive pattern generator to the incoming prbs or qrss pattern. the receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least is incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern resynchronization is initiated. automatic pattern resynchronization can be disabled. figure 9-9. prbs synchronization state diagram sync load verify 1 bit error 32 bits loaded 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 64 of 338 9.16.2 repetitive pattern synchronization repetitive pattern synchronization synchronizes the receiv e pattern generator to the incoming repetitive pattern. the receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least sis incoming bits in the current 64-bit window do not match the receive prbs pattern generator, automatic pattern resynchronization is initiat ed. automatic pattern resynchronization can be disabled. figure 9-10. repetitive pattern synchronization state diagram sync match verify 1 bit error pattern matches 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s 9.16.3 pattern monitoring pattern monitoring monitors the incoming data stream fo r out of synchronization (oos) condition, bit errors, and counts the incoming bits. an oos condition is declared when the synchronization state machine is not in the ?sync? state. an oos condition is terminated when the synchronization state machine is in the ?sync? state. bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. if they do not match, a bit error is declared, and the bit error and bit counts are incremented. if they match, only the bit count is incremented. the bit count and bit error count are not incremented when an oos condition exists. 9.16.4 pattern generation pattern generation generates the outgoing test pattern, and passes it onto error insertion. the transmit pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable. the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. qrss is programmable (on or off). for prbs and qrss patterns, the feedback is forced to one if bits 1 through 31 are all zeros. when a new pattern is loaded, the pattern generator is loaded with a pattern value before pattern generation starts. the pattern value is programmable (0 ? 2 n - 1). when prbs and qrss patterns are generated the seed value is all ones.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 65 of 338 9.16.4.1 error insertion error insertion inserts errors into the outgoing pattern data stream. errors are inserted one at a time single bit error insertion can be initiated from the microprocessor interface. if pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. pattern inversion is programmable (on or off). 9.16.4.2 performance monitoring update all counters stop counting at their maximum count. a counter register is updated by asserting (low to high transition) the performance monitoring update signal (pmu). during the counter register update process, the performance monitoring status signal (pms) is de-asserted. the counter register update process consists of loading the counter register with the current count, resetting the counter, forci ng the zero count status indication low for one clock cycle, and then asserting pms. no events shall be missed during an update procedure. 9.17 transmit packet processor the transmit packet processor accepts data from the transmit fifo, performs bit reordering, fcs processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. the data output from the transmit packet processor to the transmit serial interface is a serial data stream (bit synchronous mode). hdlc processing can be disabled (clear channel enable). disabling hdlc processing disables fcs processing, packet error insertion, stuffing, packet abort sequence insertion, and inter-frame padding. only bit reordering and packet scrambling are not disabled. bit reordering changes the bit order of each byte. if bit r eordering is disabled, the outgoing 8-bit data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is output from the transmit fifo with the msb in tfd[7] (or 15, 23, or 31) and the lsb in tfd[0] (or 8, 16, or 24) of the transmit fifo data tfd[7:0] 15:8, 23:16, or 31:24). if bit reordering is enabled, the outgoing 8-bit data stream dt[1:8] is output from the transmit fifo with the msb in tfd[0] and the lsb in tfd[7] of the transmit fifo data tfd[7:0]. in bit synchronous mode, dt [1] is the first bit transmitted. fcs processing calculates an fcs and appends it to the packet. fcs calculat ion is a crc-16 or crc-32 calculation over the entire packet. the polynomial used for fcs-16 is x 16 + x 12 + x 5 + 1. the polynomial used for fcs-32 is x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1. the fcs is inverted after calculation. the fcs type is programmable. if fcs append is enabled, the calculated fcs is appended to the packet. if fcs append is disabled, the packet is transmitted without an fcs. the fcs append mode is programmable. if packet processing is disabled, fcs processing is not performed. packet error insertion inserts errors into the fcs bytes. a single fcs bit is corrupted in each errored packet. the fcs bit corrupted is changed from errored packet to errored packet. error insertion can be controlled by a register or by the manual error insertion input ( li.tmei .tmei). the error insertion initiation type (register or input) is programmable. if a register controls error insertion, the number and frequency of the errors are programmable. if fcs append is disabled, packet error insertion will not be performed. if packet processing is disabled, packet error insertion is not performed. stuffing inserts control data into the packet to prevent packet data from mimicking flags. a packet start indication is received, and stuffing is performed until, a packet end indication is received. bit stuffing consists of inserting a '0' directly following any five contiguous '1's. if packet processing is disabled, stuffing is not performed. there is at least one flag plus a programmable number of additional flags between packets. the inter-frame fill can be flags or all '1's followed by a start flag. if the inter-frame fill is all '1's, the number of '1's between the end and start flags does not need to be an integer number of bytes, however, there must be at least 15 consecutive '1's between the end and start flags. the inter-frame padding type is programmable. if packet processing is disabled, inter-frame padding is not performed. packet abort insertion inserts a packet abort sequences as necessary. if a packet abort indication is detected, a packet abort sequence is inserted and inter-frame padding is done until a packet start flag is detected. the abort sequence is ffh. if packet processing is disabled, packet abort insertion is not performed. the packet scrambler is a x 43 + 1 scrambler that scrambles the entire packet data stream. the packet scrambler runs continuously, and is never reset. in bit synchronous mode, scrambling is performed one bit at a time. in byte synchronous mode, scrambling is performed 8 bits at a time. packet scrambling is programmable. once all packet processing has been completed serial data stream is passed on to the transmit serial interface.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 66 of 338 9.18 receive packet processor the receive packet processor accepts data from the receive serial interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, fcs error monitoring, fcs byte extraction, and bit reordering. the dat a coming from the receive serial interface is a serial data stream. packet processing can be disabled (clear channel enable). disabling packet processing disables packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, fcs error monitoring, and fcs byte extraction. only packet descrambling and bit reordering are not disabled. the packet descrambler is a self-synchronous x 43 + 1 descrambler that descrambles the entire packet data stream. packet descrambling is programmable. the descrambler runs continuously, and is never reset. the descrambling is performed one bit at a time. packet descrambling is progr ammable. if packet processing is disabled, the serial data stream is demultiplexed in to an 8-bit data stream before being passed on. if packet processing is disabled, a packet boundary is arbitrarily chosen and the data is divided into "packets" of programmable size (dependent on maximum packet size setting). these packets are then passed on to bit reordering with packet start and packet end indications. data then bypasses packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, fcs error monitoring, and fcs byte extraction. packet delineation determines the packet boundary by identifying a packet start or end flag. each time slot is checked for a flag sequence (7eh). once a flag is found, it is identified as a start/end flag and the packet boundary is set. the flag check is performed one bit at a time. if packet processing is disabled, packet delineation is not performed. inter-frame fill filtering removes the inter-frame fill between packets. when a packet end flag is detected, all data is discarded until a packet start flag is detected. the inter-frame fill can be flags or all '1's. the number of '1's between flags does not need to be an integer number of bytes, and if at least 7 '1's are detected in the first 16 bits after a flag, all data after the flag is discarded until a start flag is detected. there may be only one flag between packets. when the inter-frame fill is flags, the flags may have a shared zero (011111101111110). if there is less than 16 bits between two flags, the data is discarded. if packet processing is disabled, inter-frame fill filtering is not performed. packet abort detection searches for a packet abort sequence. between a packet start flag and a packet end flag, if an abort sequence is detected, the packet is marked with an abort indication, the aborted packet count is incremented, and all subsequent data is discarded until a packet start flag is detected. the abort sequence is seven consecutive ones. if packet processing is disabled, packet abort detection is not performed. destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. a start flag is detected, a packet start is set, the flag is discarded, destuffing is performed until an end flag is detected, a packet end is set, and the flag is discarded. in bit synchronous mode, bit destuffing is performed. bit destuffing consists of discarding any '0' that directly follows five contiguous '1's. after destuffing is completed, the serial bit stream is demultiplexed into an 8-bit parallel data stream and passed on with packet start, packet end, and packet abort indications. if there is less than eight bits in the last byte, an invalid packet flag is raised, the packet is tagged with an abort indication, and the packet size violation count is in cremented. if packet processing is disabled, destuffing is not performed. packet size checking checks each packet for a programmable maximum and programmable minimum size. as the packet data comes in, the total number of bytes is counted. if the packet length is below the minimum size limit, the packet is marked with an aborted indication, and the packet si ze violation count is incremented. if the packet length is above the maximum size limit, the packet is marked with an aborted indication, the packet size violation count is incremented, and all packet data is discarded until a packet start is received. the minimum and maximum lengths include the fcs bytes, and are determined after destuffing has occurred. if packet processing is disabled, packet size checking is not performed. fcs error monitoring checks the fcs and aborts errored packets. if an fcs error is detected, the fcs errored packet count is incremented and the packet is marked with an aborted indication. if an fcs error is not detected, the receive packet count is incremented. the fcs type (16-bit or 32-bit) is programmable. if fcs processing or packet processing is disabled, fcs error monitoring is not performed. fcs byte extraction discards the fcs bytes. if fcs extraction is enabled, the fcs bytes are extracted from the packet and discarded. if fcs extraction is disabled, the fcs bytes are stored in the receive fifo with the packet. if fcs processing or packet processing is disabled, fcs byte extraction is not performed. bit reordering changes the bit order of each byte. if bit reordering is disabled, the incoming 8-bit data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is output to the receive fifo with the msb in rfd[7]
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 67 of 338 (or 15, 23, or 31) and the lsb in rfd[0] (or 8, 16, or 24) of the receive fifo data rfd[7:0] (or 15:8, 23:16, or 31:24). if bit reordering is enabled, the incoming 8-bit data stream dt[1:8] is output to the receive fifo with the msb in rfd[0] and the lsb in rfd[7] of the receive fifo data rfd[7:0]. dt[1] is the first bit received from the incoming data stream. once all of the packet processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit parallel data stream. the receive fifo data is passed on to the receive fifo with packet start, packet end, packet abort, and modulus indications. at a packet end, the 32- bit word may contain 1, 2, 3, or 4 bytes of data depending on the number of bytes in the packet. the modulus i ndications indicate the number of bytes in the last data word of the packet. figure 9-11. hdlc encapsulation of mac frame flag(0x7e) destination adrs(da) source adrs(sa) length/type number of bytes 1 6 6 2 mac client data 46-1500 pad fcs for mac 4 fcs for hdlc flag(0x7e) 0 / 2 / 4 msb lsb
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 68 of 338 9.19 x.86 encoding and decoding x.86 protocol provides a method for encapsulating ether net frame onto laps. laps provides hdlc type framing structure for encapsulation of ethernet frames. laps encapsulated frames can be used to send data onto a sonet/sdh network. the DS33R11 expects a byte sync hronization signal to provide the byte boundary for the x.86 receiver. this is provided by the rbsy nc pin. the functional timing is shown in figure 12-4 . the x.86 transmitter provides a byte boundary indicator with the signal tbsync. the functional timing is shown in figure 12-3 . figure 9-12. laps encoding of mac frames concept ieee 802.3 mac frame laps rate adaption sdh
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 69 of 338 figure 9-13. x.86 encapsulation of the mac frame flag(0x7e) address(0x04) control(0x03) 1st octect of sapi(0xfe) 2nd octect of sapi(0x01) destination adrs(da) source adrs(sa) length/type number of bytes 1 1 1 1 1 6 6 2 mac client data 46-1500 pad fcs for mac 4 fcs for laps flag(0x7e) 4 msb lsb the DS33R11 will encode the mac frame with the laps encapsulation on a complete serial stream if configured for x.86 mode in the register li.tx86e . the DS33R11 provides the following functions:  control registers for address, control, sapih, sapil.  32 bit fcs enabled.  programmable x 43 +1 scrambling. the sequence of processing performed by the receiver is as follows:  programmable octets x 43 +1 descrambling.  detect the start flag (7e).  remove rate adaptation octets 7d, dd.  perform transparency-processing 7d, 5e is converted to 7e and 7d, 5d is converted to 7d.  check for a valid address, control and sapi fields ( li.trx86a to li.trx86sapil ).  perform fcs checking.  detect the closing flag.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 70 of 338 the x86 received frame is aborted if:  if 7d,7e is detected. this is an abort packet sequence in x.86.  invalid fcs is detected.  the received frame has less than 6 octets.  control, sapi and address field are mismatched to the programmed value.  octet 7d and octet other than 5d,5e,7e or dd is detected. for the transmitter if x.86 is enabled the sequence of processing is as follows:  construct frame including start flag, sapi, control and mac frame.  calculate fcs.  perform transparency processing - 7e is translated to 7d5e, 7d is translated to 7d5d.  append the end flag(7e).  scramble the sequence x 43 +1. note that the serial transmit and receive registers apply to the x.86 implementations with specific exceptions. the exceptions are outlined in the serial interface transmit and receive register sections.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 71 of 338 9.20 committed informati on rate controller the DS33R11 provides a cir provisioning facility. the cir can be used restricts the transport of received mac data to a programmable rate. the cir location is shown in the figure 6-1 . the cir will restrict the data flow from the receive mac to transmit hdlc. this can be used for provisioning and billing functions towards the wan. the user must set the cir register to control the amount of data throughput from the mac to hdlc transmit. the cir register is in granularity of 500kbit/s with a range of 0 to 52mbit/s. the operation of the cir is as follows:  the cir block counts the credits that are accumulated at the end of every 125ms.  if data is received and stored in the sdram to be sent to the serial interface, the interface will request the data if there is a positive credit balance. if the credi t balance is negative, transmit interface does not request data.  new credit balance is calculated credit balance = old credi t balance ? frame size in bytes after the frame is sent.  the credit balance is incremented every 125ms by cir/8.  credit balances not used in 250ms are reset to 0.  the maximum value of cir can not exceed the transmit line rate.  if the data rate received from the ethernet interface is higher than the cir, the receive queue buffers will fill and the high threshold water mark will invoke flow control to reduce the incoming traffic rate.  the cir function is only available fo r software mode of operation only.  cir function is only available in data received at the et hernet interface to be sent to wan. there is not cir functionality for data arriving from the wan to be sent to the ethernet interface.  negative credits are not allowed, if there is not a credit balance, no frames are sent until there is a credit balance again.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 72 of 338 10 integrated t1/e1/j1 transceiver 10.1 t1/e1/j1 clocks figure 10-1 shows the clock map of the t1/e1 transceiver. the routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity. figure 10-1. t1/e1/j1 clock map the tclkt mux is dependent on the state of the tcss0 and tc ss1 bits in the tr.ccr1 register and the state of the tclkt pin. transmit formatter receive framer bpclk synth remote loopback framer loopback payload loopback (see notes) ltca ltca jitter attenuator see tr.lic1 register local loopback bpclk rclk tclkt mclk rxclk txclk to liu llb = 0 llb = 1 plb = 0 plb = 1 rlb = 1 rlb = 0 flb = 1 flb = 0 jas = 0 and dja = 0 jas = 1 or dja = 1 jas = 0 or dja = 1 jas = 1 and dja = 0 rcl = 1 rcl = 0 dja = 1 dja = 0 8xclk 8 x pll pre-scaler tr.lic4.mps0 tr.lic4.mps1 tr.lic2.3 2.048 to 1.544 synthesizer b a c mclks = 0 tsysclk mclks = 1 tclkt mux
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 73 of 338 table 10-1. t1/e1/j1 transmit clock source tcss1 tcss0 transmit clock source 0 0 the tclkt pin (c) is always the source of transmit clock. 0 1 switch to the recovered clock (b) when the signal at the tclkt pin fails to transition after one channel time. 1 0 use the scaled signal (a) derived from mclk as the transmit clock. the tclkt pin is ignored. 1 1 use the recovered clock (b) as the transmit clock. the tclkt pin is ignored. 10.2 per-channel operation some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. there are five registers involved: per-channel pointer register (tr.pcpr) and per-channel data registers 1?4 (tr.pcdr1?4). the user se lects which function or functions are to be applied on a per-channel basis by setting the appropriate bit(s) in the tr.pcpr register. the user then writes to the tr.pcdr registers to select the channels for that function. the following is an example of mapping the transmit and receive bert function to channels 9?12, 20, and 21. write 11h to tr.pcpr write 00h to tr.pcdr1 write 0fh to tr.pcdr2 write 18h to tr.pcdr3 write 00h to tr.pcdr4 the user may write to the tr.pcdr1-4 with multiple func tions in the tr.pcpr register selected, but can only read the values from the tr.pcdr1-4 registers for a single func tion at a time. more information about how to use these per-channel features can be found in the tr.pcpr register. 10.3 t1/e1/j1 transceiver interrupts various alarms, conditions, and events in the t1/e1/j1 transceiver can cause interrupts. for simplicity, these are all referred to as events in this explanation. all status registers can be programmed to produce interrupts. each status register has an associated interrupt mask register. for example, tr.sr1 (status register 1) has an interrupt control register called tr.imr1 (interrupt mask register 1). status registers are the only sources of interrupts in the device. on power-up, all writeable registers of the t1/e1/j1 transceiver are automatically cleared. since bits in the tr.imrx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until the host selects which events are to product interrupts. since there are potentially many sources of interrupts on the device, several features are available to help sort out and ident ify which event is causing an interrupt. when an interrupt occurs, the host should first read the tr.iir1 and tr.iir2 registers (interrupt information registers) to identify which status register (or registers) is producing the interrupt. on ce that is determined, the individual status register or registers can be examined to determine the exact source. once an interrupt has occurred, the in terrupt handler routine should set the in tdis bit (tr.ccr3.6) to stop further activity on the interrupt pin. after all interrupts have been determined and processed, the interrupt hander routine should re-enable interrupts by setting the intdis bit = 0. note that the integrated ethernet mapper also generates interrupts, as discussed in section 9.6 .
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 74 of 338 10.4 t1 framer/formatter control and status the t1 framer portion of the transceiver is configured through a set of nine control registers. typically, the control registers are only accessed when the system is first powered up. once the transceiver has been initialized, the control registers only need to be accessed when there is a change in the system configuration. there are two receive control registers (tr.t1rcr1 and tr.t1rcr2), two transmit control registers (tr.t1tcr1 and tr.t1tcr2), and a common control register (tr.t1ccr1). each of these registers is described in this section. 10.4.1 t1 transmit transparency the software signaling insertion-enable registers, tr.ssie1? tr.ssie4, can be used to select signaling insertion from the transmit signaling registers, ts1?ts12, on a per-channel basis. setting a bit in the ssiex register allows signaling data to be sourced from the signaling registers for that channel. in transparent mode, bit 7 stuffing and/or robbed-bit signa ling is prevented from overwriting the data in the channels. if a ds0 is programmed to be clear, no robbed-bi t signaling is inserted nor does the channel have bit 7 stuffing performed. however, in the d4 framing mode, bit 2 is overwritten by a 0 when a yellow alarm is transmitted. also, the user has the option to globally override the tr.ssiex registers from determining which channels are to have bit 7 stuffing performed. if the tr.t1tcr1.3 and tr.t1tcr2.0 bits are set to 1, then all 24 t1 channels have bit 7 stuffing performed on them, regardless of how the tr.ssiex registers are programmed. in this manner, the tr.ssiex registers are only affecting the channels that are to have robbed-bit signaling inserted into them. 10.4.2 ais-ci and rai-ci generation and detection the device can transmit and detect the rai-ci and ais-ci codes in t1 mode. these codes are compatible with and do not interfere with the standard rai (yellow) and ais (blue) alarms. these codes are defined in ansi t1.403. the ais-ci code (alarm indication signal-customer installa tion) is the same for both esf and d4 operation. setting the tais-ci bit in the tr.t1ccr1 register and the tbl bit in the tr.t1tcr1 register causes the device to transmit the ais-ci code. the rais-ci status bit in the tr.sr4 register indicates the reception of an ais-ci signal. the rai-ci (remote alarm indication-customer installation) code for t1 esf operation is a special form of the esf yellow alarm (an unscheduled message). setti ng the rais-ci bit in the tr.t1ccr1 register causes the device to transmit the rai-ci code. the rai-ci code causes a standard yellow alarm to be detected by the receiver. when the host processor detects a yellow alarm, it can then test the alarm for the rai-ci state by checking the boc detector for the rai-ci flag. that flag is a 011111 code in the 6-bit boc message. the rai-ci code for t1 d4 operation is a 10001011 flag in all 24 time slots. to transmit the rai-ci code the host sets all 24 channels to idle with a 10001011 idle code. since this code meets the requirements for a standard t1 d4 yellow alarm, the host can use the receive channel monitor function to detect the 100001011 code whenever a standard yellow alarm is detected.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 75 of 338 10.4.3 t1 receive-side digita l-milliwatt code generation receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (tr.t1rdmr1/2/3) to determine which of the 24 t1 channels of the t1 line going to the backplane should be overwritten with a digital-milliwatt pattern. the digital-m illiwatt code is an 8-byte repeating pattern that represents a 1khz sine wave (1e/0b/0b/1e/9e/8b/8b/9e). each bit in the tr.t1rdmrx registers represents a particular channel. if a bit is set to a 1, then the receive data in that channel is replaced with the digital-milliwatt code. if a bit is set to 0, no replacement occurs. table 10-2. t1 alarm criteria alarm set criteria clear criteria blue alarm (ais) (note 1) when over a 3ms window, five or fewer 0s are received when over a 3ms window, six or more 0s are received yellow alarm (rai) d4 bit 2 mode (tr.t1rcr2.0 = 0) when bit 2 of 256 consecutive channels is set to 0 for at least 254 occurrences when bit 2 of 256 consecutive channels is set to 0 for fewer than 254 occurrences d4 12th f-bit mode (tr.t1rcr2.0 = 1; this mode is also referred to as the ?japanese yellow alarm?) when the 12th framing bit is set to 1 for two consecutive occurrences when the 12th framing bit is set to 0 for two consecutive occurrences esf mode when 16 consecutive patterns of 00ff appear in the fdl when 14 or fewer patterns of 00ff hex out of 16 possible appear in the fdl red alarm (lrcl) (also referred to as loss of signal) when 192 consecutive 0s are received when 14 or more 1s out of 112 possible bit positions are received note 1: the definition of blue alarm (or ais) is an unframed all-ones signal. blue alarm detectors should be able to operate properly in the presence of a 10e-3 error rate and they should not falsely trigger on a framed all-1s signal. blue alarm criteria in the device has been set to achieve this performance. it is recommended that the rbl bit be qualified with the rlos bit. note 2: ansi specifications use a different nomenclature than this document. the following terms are equivalent: rbl = ais rcl = los rlos = lof ryel = rai
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 76 of 338 10.5 e1 framer/formatter control and status the e1 framer portion of the transceiver is configured by a set of four control registers. typically, the control registers are only accessed when the system is first powered up. once the device has been initialized, the control registers need only to be accessed when there is a change in the system configuration. there are two receive control registers (tr.e1rcr1 and tr.e1rcr2) and two trans mit control registers (tr.e1tcr1 and tr.e1tcr2). there are also four status and information registers. each of these eight registers is described in this section. table 10-3. e1 sync/resync criteria frame or multiframe level sync criteria resync criteria itu spec. fas fas present in frame n and n + 2; fas not present in frame n + 1 three consecutive incorrect fas received alternate: (tr.e1rcr1.2 = 1) the above criteria is met or three consecutive incorrect bit 2 of non-fas received g.706 4.1.1 4.1.2 crc4 two valid mf alignment words found within 8ms 915 or more crc4 codewords out of 1000 received in error g.706 4.2 and 4.3.2 cas valid mf alignment word found and previous time slot 16 contains code other than all 0s two consecutive mf alignment words received in error g.732 5.2
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 77 of 338 10.5.1 automatic alarm generation the device can be programmed to automatically transmit ais or remote alarm. when automatic ais generation is enabled (tr.e1tcr2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronizati on, ais alarm (all ones) reception, or loss-of-receive carrier (or signal). the framer forces either an ais or remote alarm if any one or more of these conditions is present. when automatic rai generation is enabled (tr.e1tcr2.0 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss-of-receiv e-frame synchronization, ais alarm (all ones) reception, loss-of-receive carrier (or signal), or if crc4 multif rame synchronization cannot be found within 128ms of fas synchronization (if crc4 is enabled). if any one or more of these conditions is present, then the framer transmits an rai alarm. rai generation conforms to ets 300 011 specifications and a constant remote alarm is transmitted if the device cannot find crc4 multiframe synchronization within 400ms as per g.706. note: it is an invalid state to have both automatic ais generation and automatic remote alarm generation enabled at the same time. table 10-4. e1 alarm criteria alarm set criteria clear criteria itu specification rlos an rlos condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated by tr.e1rcr1.0 rcl 255 or 2048 consecutive 0s received as determined by tr.e1rcr2.0 at least 32 1s in 255-bit times are received g.775/g.962 rra bit 3 of nonalign frame set to 1 for three consecutive occasions bit 3 of nonalign frame set to 0 for three consecutive occasions o.162 2.1.4 rua1 fewer than three 0s in two frames (512 bits) more than two 0s in two frames (512 bits) o.162 1.6.1.2 rdma bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes v52lnk two out of three sa7 bits are 0 g.965 10.6 per-channel loopback the per-channel loopback registers (pclrs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the t1 or e1 line. if this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. one method to accomplish this is to connect rclko to tclkt and rfsync to tsync. there are no restrictions on which channels can be looped back or on how many channels can be looped back. each of the bit positions in the per-channel loopback r egisters (tr.pclr1/ tr.pclr2/ tr.pclr3/ tr.pclr4) represents a ds0 channel in the outgoing frame. when these bits are set to a 1, data from the corresponding receive channel replaces the data on tseri for that channel.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 78 of 338 10.7 error counters the transceiver contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. counter update options include one-second boundaries, 42ms (t1 mode only), 62ms (e1 mode only), or manual. see error-counter configurati on register (tr.ercnt) . when updated automatically, the user can use the interrupt from the timer to determine when to read these registers. all four counters saturate at their respective maximum counts, and they do not roll over. note: only the line-code violation count register has the potential to overflow, but the bit error would have to exceed 10e-2 before this would occur. 10.7.1 line-code violation counter (tr.lcvcr) in t1 mode, code violations are defined as bipolar violations (bpvs) or excessive 0s. if the b8zs mode is set for the receive side, then b8zs codewords are not counted. this counter is always enabled; it is not disabled during receive loss-of-synchronization (rlos = 1) conditions. table 10-5 shows what the lcvcrs count. table 10-5 t1 line code vi olation counting options count excessive zeros? (tr.ercnt.0) b8zs enabled? (tr.t1rcr2.5) counted in the lcvcrs no no bpvs yes no bpvs + 16 consecutive 0s no yes bpvs (b8zs codewords not counted) yes yes bpvs + 8 consecutive 0s in e1 mode, either bipolar violati ons or code violations can be counted. bipolar violations are defined as consecutive marks of the same polarity. in this mode, if the hdb3 mode is set for the receive side, then hdb3 codewords are not counted as bpvs. if tr.ercnt.3 is set, then the lvc counts code violations as defined in itu o.161. code violations are defined as cons ecutive bipolar violations of the same polarity. in most applications, the framer should be programmed to count bpvs when rece iving ami code and to count cvs when receiving hdb3 code. this counter increments at all times and is not disabled by loss-of-sync conditions. the counter saturates at 65,535 and does not roll over. the bit-error rate on an e1 line would have to be greater than 10 -2 before the vcr would saturate ( table 10-6 ). table 10-6. e1 line-code vi olation counting options e1 code violation select (tr.ercnt.3) counted in the lcvcrs 0 bpvs 1 cvs
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 79 of 338 10.7.2 path code violation count register (tr.pcvcr) in t1 mode, the path code violation count register record s ft, fs, or crc6 errors in t1 frames. when the receive side of a framer is set to operate in the t1 esf fram ing mode, tr.pcvcr records errors in the crc6 codewords. when set to operate in the t1 d4 framing mode, tr.pcvcr counts errors in the ft framing bit position. through the tr.ercnt.2 bit, a framer can be programmed to also report errors in the fs framing bit position. the tr.pcvcr is disabled during receive loss-of -synchronization (rlos = 1) conditions. table 10-7 shows what errors the tr.pcvcr counts. table 10-7. t1 path code vi olation counting arrangements framing mode count fs errors? counted in the pcvcrs d4 no errors in the ft pattern d4 yes errors in both the ft and fs patterns esf don?t care errors in the crc6 codewords in e1 mode, the path code violation-count register re cords crc4 errors. since the maximum crc4 count in a one- second period is 1000, this counter cannot saturate. the counter is disabled during loss-of-sync at either the fas or crc4 level; it continues to count if loss-of-multiframe sync occurs at the cas level. path code violation-count register 1 (tr.pcvcr1) is the most significant word and tr.pcvcr2 is the least significant word of a 16-bit counter that records path violations (pvs).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 80 of 338 10.7.3 frames out-of-sync count register (tr.foscr) in t1 mode, tr.foscr is used to count the number of multiframes that the receive synchronizer is out of sync. this number is useful in esf applications needing to measure the parameters loss-of-frame count (lofc) and esf error events as described in at&t publication tr54016. when tr.foscr is operated in this mode, it is not disabled during receive loss-of-synchronization (rlos = 1) conditions. tr.foscr has an alternate operating mode whereby it counts either errors in the ft framing pattern (in the d4 mode) or errors in the fps framing pattern (in the esf mode). when tr.foscr is operated in this mode, it is disabled during receive loss-of-synchronization (rlos = 1) conditions. table 10-8 shows what the foscr is capable of counting. table 10-8. t1 frames out-of-sync counting arrangements framing mode (tr.t1rcr1.3) count mos or f-bit errors (tr.ercnt.1) counted in the foscrs d4 mos number of multiframes out-of-sync d4 f-bit errors in the ft pattern esf mos number of multiframes out-of-sync esf f-bit errors in the fps pattern in e1 mode, tr.foscr counts word errors in the fas in time slot 0. this counter is disabled when rlos is high. fas errors are not counted when the framer is searching for fas alignment and/or synchronization at either the cas or crc4 multiframe level. since the maximum fas word error count in a one-second period is 4000, this counter cannot saturate. the frames out-of-sync count register 1 (tr.foscr1) is the most significant word and tr.foscr2 is the least significant word of a 16-bit counter that records frames out-of-sync. 10.7.4 e-bit counter (tr.ebcr) this counter is only available in e1 mode. e-bit count register 1 (tr.ebcr1) is the most significant word and tr.ebcr2 is the least significant word of a 16-bit counter that records far-end block errors (febe) as reported in the first bit of frames 13 and 15 on e1 lines running with crc4 multiframe. these count registers increment once each time the received e-bit is set to 0. since the maximum e-bit count in a one-second period is 1000, this counter cannot saturate. the counter is disabled during loss-of-sync at either the fas or crc4 level; it continues to count if loss-of-multiframe sync occurs at the cas level.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 81 of 338 10.8 ds0 monitoring function the transceiver has the ability to monitor one ds0 64kbps channel in the transmit direction and one ds0 channel in the receive direction at the same time. in the transmi t direction, the user determines which channel is to be monitored by properly setting the tcm0 to tcm4 bits in the tr.tds0sel register. in the receive direction, the rcm0 to rcm4 bits in the tr.rds0sel register need to be properly set. the ds0 channel pointed to by the tcm0 to tcm4 bits appear in the transmit ds0 monitor (tr.tds0 m) register. the ds0 channel pointed to by the rcm0 to rcm4 bits appear in the receive ds0 (tr.rds0m) regist er. the tcm4 to tcm0 and rcm4 to rcm0 bits should be programmed with the decimal decode of the appropriate t1or e1 channel. t1 channels 1 through 24 map to register values 0 through 23. e1 channels 1 through 32 map to register values 0 through 31. for example, if ds0 channel 6 in the transmit direction and ds0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into tr.tds0sel and tr.rds0sel: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 82 of 338 10.9 signaling operation there are two methods to access receive signaling data and provide transmit signaling data, processor-based (software-based) or hardware-based. processor-based refers to access through the transmit and receive signaling registers rs1?rs16 and ts1?ts16. hardware-based refers to the tsig and rsig pins. both methods can be used simultaneously. figure 10-2. simplified diagram of receive signaling path 10.9.1 processor-based receive signaling the robbed-bit signaling (t1) or ts16 cas signaling (e1) is sampled in the receive data stream and copied into the receive signaling registers, rs1?rs16. in t1 mode, onl y rs1?rs12 are used. the signaling information in these registers is always updated on multiframe boundaries. this function is always enabled. 10.9.1.1 change-of-state to avoid constant monitoring of the receive signaling regi sters, the transceiver can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. tr.rscse1 ? tr.rscse4 for e1 and tr.rscse1 ? tr.rscse3 for t1 are used to select which channels can cause a change-of-state indication. the change-of-state is indicated in status regi ster 5 (tr.sr1.5). if signaling integration (tr.ccr1.5) is enabled, then the new signaling state must be constant for three multiframes before a change-of-state is indicated. the user can enable the int pin to toggle low upon detecti on of a change in signaling by setting the tr.imr1.5 bit. the signaling integration mode is global and cannot be enabled on a channel-by-channel basis. the user can identity which channels have undergone a signaling change-of-state by reading the tr.rsinfo1? tr.rsinfo4 registers. the information from these registers inform the user which tr.rsx register to read for the new signaling data. all changes are indicated in the tr.rsinfo1 ? tr.rsinfo4 registers regardless of the tr.rscse1 ? tr.rscse4 registers. receive signaling registers change-of-state indication registers signaling buffers a ll-ones reinsertion control rsero rsync rsig t1/e1 data stream per-channel control signaling extraction
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 83 of 338 10.9.2 hardware-based receive signaling in hardware-based signaling the signaling data can be obtained fr om the rsero pin or the rsig pin. rsig is a signaling pcm stream output on a channel-by-channel basis from the signaling buffer. the signaling data, t1 robbed bit or e1 ts16, is still present in the original dat a stream at rsero. the signaling buffer provides signaling data to the rsig pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from t he rsync pin. in this mode, the receive elastic store can be enabled or disabled. if the receive elastic store is enabled, then the backplane clock (rsysclk) can be either 1.544mhz or 2.048mhz. in the esf framing mode, the abcd signaling bits are output on rsig in the lower nibble of each channel. the rsig data is updated once a multiframe (3ms) unless a freeze is in effect. in the d4 framing mode, the ab signaling bits are output twice on rsig in the lower nibble of each channel. hence, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each channel. the rsig data is updated once a multiframe (1.5ms) unless a freeze is in effect. see the timing diagrams in section 12 for some examples. 10.9.2.1 receive signaling reinsertion at rsero in this mode, the user provides a multiframe sync at the rsync pin and the signaling data is reinserted based on this alignment. in t1 mode, this results in two copies of the signaling data in the rsero data stream, the original signaling data and the realigned data. this is of little c onsequence in voice channels. reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. in this mode, the elastic store must be enabled; however, the backplane clock can be either 1.544mhz or 2.048mhz. signaling reinsertion can be enabled on a per-channel basis by setting the rsrcs bit high in the tr.pcpr register. the channels that will have signaling reinserted are selected by writing to the tr.pcdr1 ? tr.pcdr3 registers for t1 mode and tr.pcdr1 ? tr.pcdr4 registers fo r e1 mode. in e1 mode, the user generally selects all channels or none for reinsertion. in e1 mode, signaling reinsertion on all channels can be enabled with a single bit, tr.sigcr.7 (grsre). this bit allows the user to re insert all signaling channels without having to program all channels through the per-channel function. 10.9.2.2 force receive signaling all ones in t1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to a 1 by using the per-channel register (section 10.2 ). the user sets the btcs bit in the tr.pcpr register. the channels that will be forced to 1 are selected by writing to the tr.pcdr1 ? tr.pcdr3 registers. 10.9.2.3 receive signaling freeze the signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of synchronization (oof event), carrier loss, or frame slip. this action meets the requirements of bellcore tr?tsy? 000170 for signaling freezing. to allow this freeze action to occur, the rfe control bit (tr.sigcr.4) should be set high. the user can force a freeze by setting the rff contro l bit (tr.sigcr.3) high. the rsigf output pin provides a hardware indication that a freeze is in effect. the four-m ultiframe buffer provides a three-multiframe delay in the signaling bits provided at the rsig pin (and at the r sero pin if receive signaling reinsertion is enabled). when freezing is enabled (rfe = 1), the signaling data is held in the last-known good state until the corrupting error condition subsides. when the error condition subsides, the signaling data is held in the old state for at least an additional 9ms (or 4.5ms in d4 framing mode) before updating with new signaling data.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 84 of 338 figure 10-3. simplified diagram of transmit signaling path 10.9.3 processor-based transmit signaling in processor-based mode, signaling data is loaded into the transmit signaling registers (ts1?ts16) by the host interface. on multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. the user can employ the transmit multiframe interrupt in status register 4 (tr.sr4.4) to know when to update the signaling bits. the user need not update any transmit signaling register for which there is no change-of-state for that register. each transmit signaling register contains the robbed-bit signa ling (t1) or ts16 cas signaling (e1) for two time slots that are inserted into the outgoing stream, if enabled to do so through tr.t1tcr1.4 (t1 mode) or tr.e1tcr1.6 (e1 mode). in t1 mode, only ts1?ts12 are used. signaling data can be sourced from the tr.ts registers on a per-channel basis by using the software signaling insertion enable registers, tr.ssie1?trssie4. 10.9.3.1 t1 mode in t1 esf framing mode, there are four signaling bits per channel (a, b, c, and d). ts1?ts12 contain a full multiframe of signaling data. in t1 d4 framing mode, there are only two signaling bits per channel (a and b). in t1 d4 framing mode, the framer uses the c and d bit positions as the a and b bit positions for the next multiframe. in d4 mode, two multiframes of signaling data can be loaded into ts1?ts12. the framer loads the contents of ts1? ts12 into the outgoing shift register every other d4 multiframe. in d4 mode, the host should load new contents into ts1?ts12 on every other multiframe boundary and no later than 120s after the boundary. in t1 mode, only registers tr.ssie1?tr.ssie3 are used since there are only 24 channels in a t1 frame. transmit signaling registers signaling buffers per-channel control tser tsig t1/e1 data stream per-channel control tr.ssie1 - tr.ssie4 b7 tr.t1tcr1.4 1 0 0 1 0 1 tr.pcpr.3 only applies to t1 mode
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 85 of 338 10.9.3.2 e1 mode in e1 mode, ts16 carries the signaling information. this information can be in either ccs (common channel signaling) or cas (channel associated signaling) format. the 32 time slots are referenced by two different channel number schemes in e1. in ?channel? numbering, ts0?ts31 are labeled channels 1 through 32. in ?phone channel? numbering, ts1?ts15 are labeled channel 1 through channel 15 and ts17?ts31 are labeled channel 15 through channel 30. in e1 cas mode, the cas signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. table 10-9. time slot numbering schemes ts 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 channel 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 phone channel 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 10.9.4 hardware-based transmit signaling in hardware-based mode, signaling data is input through the tsig pin. this signaling pcm stream is buffered and inserted to the data stream being input at the tseri pin. signaling data can be inserted on a per-channel basis by the transmit hardware-signaling channel-select (thscs) function. the user has the ability to control which channels are to have signaling data from the tsig pin inserted into them on a per-channel basis. see section 10.2 for details on using this per-channel (thscs) feature. the signaling insertion capabilities of the framer are avail able whether the transmit-side elastic store is enabled or disabled. if the elastic store is enabled, the backpl ane clock (tsysclk) can be either 1.544mhz or 2.048mhz. also, if the elastic is enabled in conjunction with transmit hardware signaling, ccr3.7 must be set = 0.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 86 of 338 10.10 per-channel idle code generation channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. when operated in the t1 mode, only the first 24 channels are used by the device, the remaining channels, ch25?ch32, are not used. the device contains a 64-byte idle code array accessed by the idle array address register (tr.iaar) and the per- channel idle code register (tr.pcicr). the contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels. this substi tution can be enabled and disabled on a per-channel basis by the transmit-channel idle code-enable registers (tr.tc ice1?4) and receive-channel idle code-enable registers (tr.rcice1?4). to program idle codes, first select a channel by writing to the tr.iaar register. then write the idle code to the tr.pcicr register. for successive writes there is no need to load the tr.iaar with the next consecutive address. the tr.iaar register automatically increments after a write to the tr.pcicr register. the auto increment feature can be used for read operations as well. bits 6 and 7 of the tr.iaar register can be used to block write a common idle code to all transmit or receive positions in the array with a single write to the tr.pcicr register. bits 6 and 7 of the tr.iaar register should not be used for read operations. tr.tcice1?4 and tr.rcice1?4 are used to enable idle code replacement on a per-channel basis. table 10-10. idle-code array address mapping bits 0 to 5 of iaar register maps to channel 0 transmit channel 1 1 transmit channel 2 2 transmit channel 3 ? ? ? ? 30 transmit channel 31 31 transmit channel 32 32 receive channel 1 33 receive channel 2 34 receive channel 3 ? ? ? ? 62 receive channel 31 63 receive channel 32
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 87 of 338 10.10.1 idle-code programming examples example 1 sets transmit channel 3 idle code to 7eh . write tr.iaar = 02h ;select channel 3 in the array write tr.pcicr = 7eh ;set idle code to 7eh example 2 sets transmit channels 3, 4, 5, and 6 idle code to 7eh and enables transmission of idle codes for those channels. write tr.iaar = 02h ;select channel 3 in the array write tr.pcicr = 7eh ;set channel 3 idle code to 7eh write tr.pcicr = 7eh ;set channel 4 idle code to 7eh write tr.pcicr = 7eh ;set channel 5 idle code to 7eh write tr.pcicr = 7eh ;set channel 6 idle code to 7eh write tr.tcice1 = 3ch ;enable transmission of idle codes for channels 3,4,5, and 6 example 3 sets transmit channels 3, 4, 5, and 6 idle code to 7eh, eeh, ffh, and 7eh, respectively. write tr.iaar = 02h write tr.pcicr = 7eh write tr.pcicr = eeh write tr.pcicr = ffh write tr.pcicr = 7eh example 4 sets all transmit idle codes to 7eh. write tr.iaar = 4xh write tr.pcicr = 7eh example 5 sets all receive and transmit idle codes to 7eh and enables idle code substitution in all e1 transmit and receive channels. write tr.iaar = cxh ;enable block write to all transmit and receive positions in the array write tr.pcicr = 7eh ;7eh is idle code write tr.tcice1 = feh ;enable idle code substitution for transmit channels 2 through 8 ;although an idle code was programmed for channel 1 by the block write ;function above, enabling it for channel 1 would step on the frame ;alignment, alarms, and sa bits write tr.tcice2 = ffh ;enable idle code substitution for transmit channels 9 through 16 write tr.tcice3 = feh ;enable idle code substitution for transmit channels 18 through 24 ;although an idle code was programmed for channel 17 by the block write ;function above, enabling it for channel 17 would step on the cas frame ;alignment, and signaling information write tr.tcice4 = ffh ;enable idle code substitution for transmit channels 25 through 32 write tr.rcice1 = feh ;enable idle code substitution for receive channels 2 through 8 write tr.rcice2 = ffh ;enable idle code substitution for receive channels 9 through 16 write tr.rcice3 = feh ;enable idle code substitution for receive channels 18 through 24 write tr.rcice4 = ffh ;enable idle code substitution for receive channels 25 through 32 the transmit-channel idle-code enable registers (tr.tcice1/2/3/4) are used to determine which of the 24 t1 or 32 e1 channels from the backplane to the t1 or e1 line s hould be overwritten with the code placed in the per-channel code array. the receive-channel idle-code enable registers (tr.rcice1/2/3/4) are used to determine which of the 24 t1 or 32 e1 channels from the backplane to the t1 or e1 line s hould be overwritten with the code placed in the per-channel code array.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 88 of 338 10.11 channel blocking registers the receive channel blocking registers (tr.rcbr1/t r.rcbr2/tr.rcbr3/tr.rcbr4) and the transmit channel blocking registers (tr.tcbr1/tr.tcbr2/tr.tcbr 3/tr.tcbr4) control rchb lk and tchblk pins, respectively. the rchblk and tchblk pi ns are user-programmable outputs that can be forced either high or low during individual channels. these outputs can be used to block clocks to a usart or lapd controller in isdn-pri applications. when the appropriate bits are set to a 1, the rchblk and tchblk pins are held high during the entire corresponding channel time. channels 25 through 32 are ignored when the device is operated in the t1 mode. 10.12 elastic stores operation the device contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. both elastic stores are fully independent. the transmit and receive-side elastic stores can be enabled/disabled independently of each other. also, each elastic store can interface to either a 1.544mhz or 2.048mhz/4.096mhz/ 8.192mhz/16.384mhz backplane without regard to the backplane rate the other elastic store is interfacing to. the elastic stores have two main purposes. firstly, they can be used for rate conversion. when the device is in the t1 mode, the elastic stores can rate-convert the t1 data stream to a 2.048mhz backplane. in e1 mode, the elastic store can rate-convert the e1 data stream to a 1.544mhz backplane. secondly, they can be used to absorb the differences in frequency and phase between the t1 or e1 data stream and an asynchronous (i.e., not locked) backplane clock, which can be 1.544mhz or 2.048mhz. in this mode, the elastic stores manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. the elastic stores can also be used to multiplex t1 or e1 data streams into higher backplane rates. 10.12.1 receive elastic store see the tr.iocr1 and tr.iocr2 registers for information about clock and i/o configurations. if the receive-side elastic store is enabled, then the user must provide either a 1.544mhz or 2.048mhz clock at the rsysclk pin. the user has the option of either providing a frame/multiframe sync at the rsync pin or having the rsync pin provide a pulse on frame/multiframe boundaries. if signaling reinsertion is enabled, signaling data in ts16 is realigned to the multiframe sync input on rsync. otherwise, a multiframe sync input on rsync is treated as a simple frame boundary by the elastic store. the framer always indicate s frame boundaries on the network side of the elastic store by the rfsync output, whether the elastic store is enabled or not. multiframe boundaries are always indicated by the rmsync output. if the elastic store is enabled, then rmsync outputs the multiframe boundary on the backplane side of the elastic store. 10.12.1.1 t1 mode if the user selects to apply a 2.048mhz clock to the rsysclk pin, then the data output at rsero is forced to all 1s every fourth channel and the f-bit is passed into the msb of ts0. hence, channels 1 (bits 1?7), 5, 9, 13, 17, 21, 25, and 29 [time slots 0 (bits 1?7), 4, 8, 12, 16, 20, 24, and 28] are forced to a 1. also, in 2.048mhz applications, the rchblk output is forced high during the same channels as the rsero pin. this is useful in t1-to-e1 conversion applications. if the two-frame elastic buffer either fills or empties, a controlled slip occurs. if the buffer empties, then a full frame of data is repeated at rsero, and the tr.sr5.0 and tr.sr5.1 bits are set to a 1. if the buffer fills, then a full frame of data is deleted, and the tr.sr5.0 and tr.sr5.2 bits are set to a 1. 10.12.1.2 e1 mode if the elastic store is enabled, then either cas or crc4 multiframe boundar ies are indicated through the rmsync output. if the user selects to apply a 1.544mhz clock to t he rsysclk pin, then every fourth channel of the received e1 data is deleted and an f-bit position, which is forced to 1, is inserted. hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are deleted from the received e1 data stream. also, in 1.544mhz applications, the rchblk output is not active in channels 25 through 32 (i.e., rcbr4 is not active). if the two-frame elastic buffer either fills or empties, a controlled slip occurs. if the buffer empties, then a full frame of data is repeated at rsero, and the tr.sr5.0 and tr.sr5.1 bits are set to a 1. if the buffer fills, then a full frame of data is deleted, and the tr.sr5.0 and tr.sr5.2 bits are set to a 1.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 89 of 338 10.12.2 transmit elastic store see the tr.iocr1 and tr.iocr2 registers for information about clock and i/o configurations. the operation of the transmit elastic store is very similar to the receive side. if the transmit-side elastic store is enabled, a 1.544mhz or 2.048mhz clock can be applied to the tsysclk input. controlled slips in the transmit elastic store are reported in the tr.sr5.3 bit, and the direction of the slip is report ed in the tr.sr5.4 and tr.sr5.5 bits. if hardware signaling insertion is not enabled, tr.ccr3.7 should be set = 1. 10.12.2.1 t1 mode if the user selects to apply a 2.048mhz clock to the tsysclk pin, then the data input at tseri is ignored every fourth channel. therefore channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are ignored. the user can supply frame or multiframe sync pulse to the tssync input. also, in 2.048mhz applications, the tchblk output is forced high during the channels ignored by the framer. 10.12.2.2 e1 mode a 1.544mhz or 2.048mhz clock can be applied to the tsysclk input. the user must supply a frame sync pulse or a multiframe sync pulse to the tssync input. 10.12.3 elastic stores initialization there are two elastic store initializations that can be us ed to improve performance in certain applications, elastic store reset and elastic store align. both of these invo lve the manipulation of the elastic store?s read and write pointers and are useful primarily in synchronous applications (rsysclk/tsysclk are locked to rclko/tclkt, respectively) ( table 10-11 ). table 10-11. elastic store delay after initialization initialization register bit delay receive elastic store reset transmit elastic store reset tr.escr.2 tr.escr.6 8 clocks < delay < 1 frame 1 frame < delay < 2 frames receive elastic store align transmit elastic store align tr.escr.3 tr.escr.7 ? frame < delay < 1 ? frames ? frame < delay < 1 ? frames 10.12.4 minimum delay mode elastic store minimum delay mode can be used when the elasti c store?s system clock is locked to its network clock (i.e., rclko locked to rsysclk for the receive side and tclkt locked to tsysclk for the transmit side). tr.escr.5 and tr.escr.1 enable the transmit and receiv e elastic store minimum delay modes. when enabled, the elastic stores are forced to a maximum depth of 32 bits instead of the normal two-frame depth. this feature is useful primarily in applications that interface to a 2. 048mhz bus. certain restrictions apply when minimum delay mode is used. in addition to the restriction mentioned above, rsync must be configured as an output when the receive elastic store is in minimum delay mode; tsy nc must be configured as an output when transmit minimum delay mode is enabled. in a typical application, rsysclk and tsysclk are locked to rclko, and rsync (frame output mode) is connected to tssync (frame input mode). all of the slip contention logic in the framer is disabled (since slips cannot occur). on power-up, after the rsysclk and tsysclk signals have locked to their respective network clock signals, the elastic store reset bits (tr. escr.2 and tr.escr.6) should be toggled from a 0 to a 1 to ensure proper operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 90 of 338 10.13 g.706 intermediate crc-4 updating (e1 mode only) the device can implement the g.706 crc-4 recalculation at intermediate path points. when this mode is enabled, the data stream presented at tser i already has the fas/nfas, crc mu ltiframe alignment word, and crc-4 checksum in time slot 0. the user can modify the sa bit positions. this change in data content is used to modify the crc-4 checksum. this modification, however, does not corr upt any error information the original crc-4 checksum may contain. in this mode of operation, tsync must be configured to multiframe mode. the data at tseri must be aligned to the tsync signal. if tsync is an input, then the user must assert tsync aligned at the beginning of the multiframe relative to tseri. if tsync is an output, the user must multiframe-align the data presented to tseri. figure 10-4. crc-4 recalculate method tser xor crc-4 calculator extract old crc-4 code insert new crc-4 code modify sa bit positions new sa bit data + tposo/tnego
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 91 of 338 10.14 t1 bit-oriented code (boc) controller the transceiver contains a boc generator on the transmit side and a boc detector on the receive side. the boc function is available only in t1 mode. 10.14.1 transmit boc bits 0 to 5 in the tr.tfdl register contain the boc message to be transmitted. setting tr.bocc.0 = 1 causes the transmit boc controller to immediately begin inserting t he boc sequence into the fdl bit position. the transmit boc controller automatically provides the abort sequence. boc messages are transmitted as long as tr.bocc.0 is set. transmit a boc 1) write 6-bit code into the tr.tfdl register. 2) set the sboc bit in tr.bocc = 1. 10.15 receive boc the receive boc function is enabled by setting tr.bocc.4 = 1. the tr.rfdl register now operates as the receive boc message and information register. the lower six bits of the tr.rfdl register (boc message bits) are preset to all 1s. when the boc bits change state, the boc change-of-state indicator, tr.sr8.0, alerts the host. the host then reads the tr.rfdl register to get the boc status and message. a change-of-state occurs when either a new boc code has been present for a time determined by the receive boc filter bits rbf0 and rbf1 in the tr.bocc register, or a nonvalid code is being received. receive a boc 1) set integration time through tr.bocc.1 and tr.bocc.2. 2) enable the receive boc function (tr.bocc.4 = 1). 3) enable interrupt (tr.imr8.0 = 1). 4) wait for interrupt to occur. 5) read the tr.rfdl register. 6) if tr.sr2.7 = 1, then a valid boc message was received. the lower six bits of the tr.rfdl register comprise the message.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 92 of 338 10.16 additional (sa) and international (si) bit operation (e1 only) when operated in the e1 mode, the transceiver provides two methods for accessing the sa and the si bits. the first method involves using the internal tr.raf/ tr.rnaf and tr.taf/ tr.tnaf registers (section 10.16.1 ). the second method, which is covered in section 10.16.2 , involves an expanded version of the first method. 10.16.1 method 1: internal register scheme based on double-frame on the receive side, the tr.raf and tr.rnaf registers alwa ys report the data as it received in the sa and si bit locations. the tr.raf and tr.rnaf registers are updated on align-frame boundaries. the setting of the receive align frame bit in status register 4 (tr.sr4.0) indi cates that the contents of the tr.raf and tr.rnaf have been updated. the host can use the tr.sr4.0 bit to know when to read the tr.raf and tr.rnaf registers. the host has 250s to retrieve the data before it is lost. on the transmit side, data is sampled from the tr.taf and tr.tnaf registers with the setting of the transmit align frame bit in status register 4 (tr.sr4.3). the host can use the tr.sr4.3 bit to know when to update the tr.taf and tr.tnaf registers. it has 250s to update the data or else the old data is retransmitted . if the tr.taf and tr.tnaf registers are only being used to source the align frame and nonalign frame-sync patterns, then the host need only write once to these registers . data in the si bit position is overwritten if either the framer is (1) programmed to source the si bits from the tseri pin, (2) in the crc4 mode, or (3) has automatic e-bit insertion enabled. data in the sa bit position is overwritt en if any of the tr.e1tcr2.3 to tr.e1tcr2.7 bits are set to 1. 10.16.2 method 2: internal register scheme based on crc4 multiframe the receive side contains a set of eight registers (tr. rsiaf, tr.rsinaf, tr.rra, and tr.rsa4 ? tr.rsa8) that report the si and sa bits as they ar e received. these registers are updated with the setting of the receive crc4 multiframe bit in status register 2 (tr.sr4.1). the host can use the tr.sr4.1 bit to know when to read these registers. the user has 2ms to retrieve the data before it is lost. the msb of each register is the first received. see the following register descriptions for more details. the transmit side also contains a set of eight register s (tr.tsiaf, tr.tsinaf, tr.tra, and tr.tsa4 ? tr.tsa8) that, through the transmit sa bit control register (tr.tsacr), can be programmed to insert si and sa data. data is sampled from these registers with the setting of the transmit multiframe bit in status register 2 (tr.sr4.4). the host can use the tr.sr4.4 bit to know when to update these registers. it has 2ms to update the data or else the old data is retransmitted. the msb of each register is the first bit transmitted. see the register descriptions for more details.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 93 of 338 10.17 additional hdlc controllers in t1/e1/j1 transceiver this device has two enhanced hdlc controllers, hdlc #1 and hdlc #2. each controller is configurable for use with time slots, sa4 to sa8 bits (e1 mode), or the fdl (t1 mode). each hdlc controller has 128-byte buffers in the transmit and receive paths. when used with time slots, the user can select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits within the time slot(s) to assign to the hdlc controllers. the user must not map both transmit hdlc controllers to the same sa bits, time slots or, in t1 mode, map both controllers to the fdl. hdlc #1 and hdlc #2 are identical in operation and therefore the following operational description refers only to a singular controller. the hdlc controller performs the entire necessary overhead for generating and receiving performance report messages (prms) as described in ansi t1.403 and the messages as described in at&t tr54016. the hdlc controller automatically generates and detects flags, generates and checks the crc check sum, generates and detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. the 128-byte buffers in the hdlc controller are large enough to allow a full prm to be received or transmitted without host intervention. the hdlc registers are divided into four groups: control/ configuration, status/information, mapping, and fifos. table 10-12 lists these registers by group. 10.17.1 hdlc configuration the tr.hxtc and tr.hxrc registers perform the basic configuration of the hdlc controllers. operating features such as crc generation, zero stuffer, transmit and receive hdlc mapping options, and idle flags are selected here. these registers also reset the hdlc controllers.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 94 of 338 table 10-12. hdlc controller registers register function control and configuration tr.h1tc , hdlc #1 transmit control register tr.h2tc , hdlc #2 transmit control register general control over the transmit hdlc controllers tr.h1rc , hdlc #1 receive control register tr.h2rc , hdlc #2 receive control register general control over the receive hdlc controllers tr.h1fc , hdlc #1 fifo control register tr.h2fc , hdlc #2 fifo control register sets high watermark for receiver and low watermark for transmitter status and information tr.sr6 , hdlc #1 status register tr.sr7 , hdlc #2 status register key status information for both transmit and receive directions tr.imr6 , hdlc #1 interrupt mask register tr.imr7 , hdlc #2 interrupt mask register selects which bits in the status registers (sr7 and sr8) cause interrupts tr.info4 , hdlc #1 and #2 information register tr.info5 , hdlc #1 information register tr.info6 , hdlc #2 information register information about hdlc controller tr.h1rpba , hdlc #1 receive packet bytes available tr.h2rpba , hdlc #2 receive packet bytes available indicates the number of bytes that can be read from the receive fifo tr.h1tfba , hdlc #1 transmit fifo buffer available tr.h2tfba , hdlc #2 transmit fifo buffer available indicates the number of bytes that can be written to the transmit fifo mapping tr.h1rcs1, tr.h1rcs2, tr.h1rcs3, tr.h1rcs4, hdlc #1 receive channel select registers tr.h2rcs1, tr.h2rcs2, tr.h2rcs3, tr.h2rcs4, hdlc #2 receive channel select registers selects which channels are mapped to the receive hdlc controller tr.h1rtsbs, hdlc #1 receive ts/sa bit select tr.h2rtsbs, hdlc #2 receive ts/sa bit select selects which bits in a channel are used or which sa bits are used by the receive hdlc controller tr.h1tcs1, tr.h1tcs2, tr.h1tcs3, tr.h1tcs4, hdlc #1 transmit channel select registers tr.h2tcs1, tr.h2tcs2, tr.h2tcs3, tr.h2tcs4, hdlc #2 transmit channel select registers selects which channels are mapped to the transmit hdlc controller tr.h1ttsbs, hdlc # 1 transmit ts/sa bit select tr.h2ttsbs, hdlc # 2 transmit ts/sa bit select selects which bits in a channel are used or which sa bits are used by the transmit hdlc controller fifos tr.h1rf , hdlc #1 receive fifo register tr.h2rf , hdlc #1 receive fifo register access to 128-byte receive fifo tr.h1tf , hdlc #1 transmit fifo register tr.h2tf , hdlc #2 transmit fifo register access to 128-byte transmit fifo
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 95 of 338 10.17.2 fifo control the fifo control register (tr.hxfc) controls and sets the watermarks for the transmit and receive fifos. bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. when the transmit fifo empties below the low watermark, the tlwm bit in the appropriate hdlc status register tr.sr6 or tr.sr7 is set. tlwm is a real-time bit and remains set as long as the transmit fifo?s read pointer is below the watermark. if enabled, this condition can also cause an interrupt through the int pin. when the receive fifo fills above the high watermark, the rhwm bit in the appropriate hdlc status register is set. rhwm is a real-time bit and remains set as long as the receive fifo?s write pointer is above the watermark. if enabled, this condition can also cause an interrupt through the int pin. 10.17.3 hdlc mapping the hdlc controllers must be assigned a space in the t1/e1 bandwidth in which they transmit and receive data. the controllers can be mapped to either the fdl (t1), sa bits (e1), or to channels. if mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to an hdlc controller. when assigned to a channel(s), any combination of bits within the channel(s) can be avoided. the tr.hxrcs1 ? tr.hxrcs4 registers are used to assign the receive controllers to channels 1?24 (t1) or 1?32 (e1) according to the following table: register channels tr.hxrcs1 1?8 tr.hxrcs2 9?16 tr.hxrcs3 17?24 tr.hxrcs4 25?32 the tr.hxtcs1 ? tr.hxtcs4 registers are used to assign the transmit controllers to channels 1?24 (t1) or 1?32 (e1) according to the following table. register channels tr.hxtcs1 1?8 tr.hxtcs2 9?16 tr.hxtcs3 17?24 tr.hxtcs4 25?32
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 96 of 338 10.17.4 fifo information the transmit fifo buffer-available register indicates the number of bytes that can be written into the transmit fifo. the count form this register informs the host as to how many bytes can be written into the transmit fifo without overflowing the buffer. 10.17.5 receive packet-bytes available the lower 7 bits of the receive packet-bytes available r egister indicates the number of bytes (0 through 127) that can be read from the receive fifo. the value indicated by th is register (lower seven bits) informs the host as to how many bytes can be read from the receive fifo without going past the end of a message. this value refers to one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. after reading the number of bytes indicated by this register, the host then checks the hdlc information register for detailed message status. if the value in the tr.hxrpba register refers to the beginning portion of a message or continuation of a message, then the msb of the tr.hxrpba register returns a value of 1. this indicates that the host can safely read the number of bytes returned by the lower seven bits of the tr.hxrpba register, but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise). 10.17.5.1 receive hdlc code example the following is an example of a receive hdlc routine: 1) reset receive hdlc controller. 2) set hdlc mode, mapping, and high watermark. 3) start new message buffer. 4) enable rpe and rhwm interrupts. 5) wait for interrupt. 6) disable rpe and rhwm interrupts. 7) read tr.hxrpba register. n = tr.hxrpba (lower 7 bits are byte count, msb is status). 8) read (n and 7fh) bytes from receive fifo and store in message buffer. 9) read tr.info5 register. 10) if ps2, ps1, ps0 = 000, then go to step 4. 11) if ps2, ps1, ps0 = 001, then packet terminated ok, save present message buffer. 12) if ps2, ps1, ps0 = 010, then packet terminated with crc error. 13) if ps2, ps1, ps0 = 011, then packet aborted. 14) if ps2, ps1, ps0 = 100, then fifo overflowed. 15) go to step 3.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 97 of 338 10.18 legacy fdl support (t1 mode) 10.18.1 overview to provide backward compatibility to the older ds21x52 t1 device, the transceiver maintains the circuitry that existed in the previous generation of the t1 framer. in new applications, it is recommended that the hdlc controllers and boc controller described in section 10.14 and 10.17 are used. 10.18.2 receive section in the receive section, the recovered fdl bits or fs bi ts are shifted bit-by-bit into the receive fdl register (tr.rfdl). because the tr.rfdl is 8 bits in length, it fills up every 2ms (8 x 250s). the framer signals an external microcontroller that the buffer has filled through the tr.sr8.3 bit. if enabled through tr.imr8.3, the int pin toggles low, indicating that the buffer has filled and needs to be read. the user has 2ms to read this data before it is lost. if the byte in the tr.rfdl matches either of the bytes programmed into the tr.rfdlm1 or tr.rfdlm2 registers, then the tr.sr8.1 bit is set to a 1 and the int pin toggles low if enabled through tr.imr8.1. this feature allows an external microcontroller to ignore the fdl or fs pattern until an important event occurs. the framer also contains a zero destuffer, which is controlled through the tr.t1rcr2.3 bit. in both ansi t1.403 and tr54016, communications on the fdl follows a subset of an lapd protocol. the lapd protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal ( 11111111). if enabled through tr.t1rcr2.3, the device automatically looks for five 1s in a row, followed by a 0. if it finds such a pattern, it automatically removes the zero. if the zero destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. the tr.t1rcr2.3 bit should always be set to a 1 when the device is extracting the fdl. refer to application note 335: ds2141a, ds2151 controlling the fdl for information about using the device in fdl applications in this legacy support mode.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 98 of 338 10.18.3 transmit section the transmit section shifts out into the t1 data stream either the fdl (in the esf framing mode) or the fs bits (in the d4 framing mode) contained in the transmit fdl register (tr.tfdl). when a new value is written to tr.tfdl, it is multiplexed serially (lsb first) into the proper position in the outgoing t1 data stream. after the full 8 bits have been shifted out, the framer signals the host microcontroller by setting the tr.sr8.2 bit to a 1 that the buffer is empty and that more data is needed. the int also toggles low if enabled through tr.imr8.2. the user has 2ms to update tr.tfdl with a new value. if tr.tfdl is not updated, the old value in tr.tfdl is transmitted once again. the framer also contains a zero stuffer that is controlled through the tr.t1tcr2.5 bit. in both ansi t1.403 and tr54016, communications on the fdl follows a subset of an lapd protocol. the lapd protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). if enabled through tr.t1tcr2.5, the framer automatically looks for five 1s in a row. if it finds such a pattern, it automatically inserts a 0 after the five 1s. the tr.t1tcr2.5 bit should always be set to a 1 when the framer is inserting the fdl. 10.19 d4/slc-96 operation in the d4 framing mode, the framer uses the tr.tfdl register to insert the fs framing pattern. to allow the device to properly insert the fs framing pattern, the tr.tfdl register at address c1h must be programmed to 1ch and the following bits must be programmed as shown: tr.t1tcr1.2 = 0 (source fs data from the tr.tfdl register) tr.t1tcr2.6 = 1 (allow the tr.tfdl register to load on multiframe boundaries) since the slc-96 message fields share the fs-bit position, the user can access these message fields through the tr.tfdl and tr.rfdl registers. refer to application note 345: ds2141a, ds2151, ds2152 slc-96 for a detailed description about implementing an slc-96 function.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 99 of 338 10.20 programmable in-band loop code generation and detection the transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. this function is available only in t1 mode. to transmit a pattern, the user loads the pattern into the transmit code-definition registers (tr.tcd1 and tr.tcd2) and selects the proper length of the pattern by setting the tc0 and tc1 bits in the in-band code control (tr.ibcc) register. when generating a 1-, 2-, 4-, 8-, or 16-bit pattern, both transmit code-definition registers must be filled with the proper code. generation of a 3-, 5-, 6-, and 7- bit pattern only requires tr.tcd1 to be filled. once this is accomplished, the pattern is transmitted as long as the tloop control bit (tr.t1ccr1.0) is enabled. normally (unle ss the transmit formatter is programmed to not insert the f-bit position) the framer overwrites the repeating pattern once every 193 bits to send the f-bit position. for example, to transmit the standard ?loop-up? code for csus, which is a repeating pattern of ...10000100001... , set tr.tcd1 = 80h, tr.ibcc = 0, and tr.t1ccr1.0 = 1. the framer has three programmable pattern detectors. typically two of the detectors are used for ?loop-up? and ?loop-down? code detection. the user programs the codes to be detected in the receive up-code definition (tr.rupcd1 and tr.rupcd2) registers and the rece ive down-code definition (tr.rdncd1 and tr.rdncd2) registers, and the length of each pattern is selected through the tr.ibcc register. there is a third detector (spare) that is defined and controlled through the tr.rscd1/ tr .rscd2 and tr.rscc registers. when detecting a 16-bit pattern, both receive code-definition registers are used toget her to form a 16-bit register. for 8-bit patterns, both receive code-definition registers are filled with the same val ue. detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code-definition register to be filled. the framer detects repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10e-2. the detectors are capable of handling both f-bit inserted and f-bit overwrite patterns. writing t he least significant byte of the receive code-definition register resets the integration period for that detector. the code detector has a nominal integration period of 36ms. hence, after about 36ms of receiving a valid code, the proper status bit (lup at tr.sr3.5, ldn at tr.sr3.6, and lspare at tr.sr3.7) is set to a 1. normally codes are sent for a period of five seconds. it is recommended that the software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure the code is continuously present.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 100 of 338 10.21 line interface unit (liu) the liu contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the t1 line, and the jitter attenuator. these three sections are controlled by the line interface control registers (lic1?lic4), which are described in the following sections. the liu has its own t1/e1 mode-select bit and can operate independently of the framer function. the transceiver can switch between t1 or e1 networks without changing external components on the transmit or receive side. figure 10-7 shows a network connection using minimal components. in this configuration, the transceiver can connect to t1, j1, or e1 (75  or 120  ) without component changes. the receiver can adjust the 120  termination to 100  or 75  . the transmitter can adjust its output impedance to provide high return-loss characteristics for 120  , 100  , and 75  lines. other components can be added to this configuration to meet safety and network protection requirements (section 10.25 ). 10.21.1 liu operation the analog ami/hdb3 waveform off the e1 line or the ami/b8zs waveform off of the t1 line is transformer-coupled into the rtip and rring pins of the device. the user has the option to use internal termination, software selectable for 75  /100  /120  applications, or external termination. the liu recovers clock and data from the analog signal and passes it through the jitter-attenuation mux outputting the received line clock at rdclko and bipolar or nrz data at rposo and rnego. the transceiver c ontains an active filter that reconstructs the analog- received signal for the nonlinear losses that occur in trans mission. the receive circuitry also is configurable for various monitor applications. the device has a usable receiv e sensitivity of 0db to -43db for e1 and 0db to -36db for t1, which allow the device to operate on 0.63mm (22awg) cables up to 2.5km (e1) and 6k feet (t1) in length. data input at tposi and tnegi is sent through the jitter-attenuation mux to the waveshaping circuitry and line driver. the transceiver drives the e1 or t1 line from the ttip and tring pins through a coupling transformer. the line driver can handle both cept 30/isdn-pri lines for e1 and long-haul (csu) or short-haul (dsx-1) lines for t1. 10.21.2 receiver the receiver contains a digital clock recovery system. t he device couples to the receive e1 or t1 twisted pair (or coaxial cable in 75  e1 applications) through a 1:1 transformer. see table 10-13 for transformer details. the device has the option of using software-selectable term ination requiring only a single fixed pair of termination resistors. the transceiver?s liu is designed to be fully software selectable for e1 and t1, requiring no change to any external resistors for the receive side. the receive side allows the user to configure the transceiver for 75  , 100  , or 120  receive termination by setting the rt1 (tr.lic4.1) and rt0 (tr.lic4.0) bits. when using the internal termination feature, the resistors labeled r in figure 10-7 should be 60  each. if external termination is used, rt1 and rt0 should be set to 0 and the resistors labeled r in figure 10-7 should be 37.5  , 50  , or 60  each, depending on the line impedance. there are two ranges of user-selectable receive sensitivity for t1 and e1. the egl bit of tr.lic1 (tr.lic1.4) selects the full or limited sensitivity. the resultant e1 or t1 clock derived from mclk is multiplied by 16 through an internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16-times over-sampler that is used to recover the clock and data. this over-sampling technique offers outstanding performance to meet jitter tolerance specifications shown in figure 10-10 . normally, the clock that is output at the rclko pin is the recovered clock from the e1 ami/hdb3 or t1 ami/b8zs waveform presented at the rtip and rring inputs. if the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the rclko to an approximate 50% duty cycle. if the jitter attenuator is either placed in the transmit path or is di sabled, the rclko output can exhibit slightly shorter high cycles of the clock. this is because of the highly ov er-sampled digital-clock recovery circuitry. see the receive ac timing characteristics in section 13.9 for more details. when no signal is present at rtip and rring, a receive carrier loss (rcl) condition occurs and the rclko is derived from the jaclk source.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 101 of 338 10.21.2.1 receive level indicator and threshold interrupt the device reports the signal strength at rtip and rring in 2.5db increments through rl3?rl0 located in information register 2 (tr.info2). this feature is helpful when trouble-shooting line-performance problems. the device can initiate an interrupt whenever the input falls below a certain level through the input-level under-threshold indicator (tr.sr1.7). using the rlt0?rlt4 bits of the tr .ccr4 register, the user can set a threshold in 2.5db increments. the tr.sr1.7 bit is set whenever the input le vel at rtip and rring falls below the threshold set by the value in rlt0?rlt4. the level must remain below the programmed threshold for approximately 50ms for this bit to be set. the accuracy of the receive level indication is 1 lsb (2.5db) from 25c to 85c and 2 lsbs (5db) from ?40c to 25c. 10.21.2.2 receive g.703 synchronization signal (e1 mode) the transceiver is capable of receiving a 2.048mhz square-wa ve synchronization clock as specified in section 13 of itu g.703, october 1998. in order to use the device in this mode, set the receive synchronization clock enable (tr.lic3.2) = 1. 10.21.2.3 monitor mode monitor applications in both e1 and t1 require various flat gain settings for the receive-side circuitry. the device can be programmed to support these applications through the monitor mode control bits mm1 and mm0 in the tr.lic3 register ( figure 10-5 ). figure 10-5. typical monitor application primary t1/e1 terminating device monitor port jack t1/e1 line x f m r t1/e1 xcvr rt rm rm secondary t1/e1 terminating device
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 102 of 338 10.21.3 transmitter the transceiver uses a phase-lock loop along with a prec ision digital-to-analog converter (dac) to create the waveforms that are transmitted onto the e1 or t1 line. the waveforms created by the device meet the latest etsi, itu, ansi, and at&t specifications. the user selects which waveform is generated by setting the ets bit (tr.lic2.7) for e1 or t1 operation, then programming the l2/l1/l0 bits in register tr.lic1 for the appropriate application. a 2.048mhz or 1.544mhz clock is required at tdclki for transmitting data presented at tposi and tnegi. normally these pins are connected to tclko, tposo, and tnego. however, the liu can operate in an independent fashion. itu specification g.703 requires an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specifications require an accuracy of 32ppm for t1 interfaces. the clock can be sourced internally from rclko or jaclk. see tr.lic2.3, tr.lic4.4, and tr.lic4.5 for details. because of the nature of the transmitter?s design, very little jitter (less than 0.005ui p-p broadband from 10hz to 100khz) is added to the jitter present on tclkt. also, the waveforms created are independent of the duty cycle of tclkt. the transmitter in the device couples to the e1 or t1 transmit twisted pair (or coaxial cable in some e1 applications) through a 1:2 step-up transformer. for the device to create the proper waveforms, the transformer used must meet the specifications listed in table 10-13 . the device has the option of using soft ware-selectable transmit termination. the transmit line drive has two modes of operation: fixed gain or automatic gain. in the fixed gain mode, the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. in the automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the network load. see the transmit line build-out control (tr.tlbc) register for details. 10.21.3.1 transmit short-circuit detector/limiter the device has an automatic short-circuit limiter that limits the source current to 50ma (rms) into a 1 ? load. this feature can be disabled by setting the scld bit (tr.lic2.1) = 1. tcle (tr.info2.5) provides a real-time indication of when the current limiter is activated. if the current limit er is disabled, tcle indicate s that a short-circuit condition exists. status register tr.sr1.2 provides a latched vers ion of the information, which can be used to activate an interrupt when enabled by the tr.imr1 register. the tpd bit (tr.lic1.0) powers down the transmit line driver and three-states the ttip and tring pins. 10.21.3.2 transmit open-circuit detector the device can also detect when the ttip or tring outputs are open circuited. tocd (tr.info2.4) provides a real-time indication of when an open circuit is detected. tr.sr1 provides a latched version of the information (tr.sr1.1), which can be used to activate an interrupt when enabled by the tr.imr1 register. 10.21.3.3 transmit bpv error insertion when ibpv (tr.lic2.5) is transitioned from a 0 to a 1, the device waits for the next occurrence of three consecutive 1s to insert a bpv. ibpv must be cleared and set again for another bpv error insertion. 10.21.3.4 transmit g.703 synchronization signal (e1 mode) the transceiver can transmit the 2.048mhz square-wave synchronization clock as specified in section 13 of itu g.703, october 1998. in order to transmit the 2.048mhz clock, when in e1 mode, set the transmit synchronization clock enable (tr.lic3.1) = 1.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 103 of 338 10.22 mclk prescaler a 16.384mhz, 8.192mhz, 4.096mhz, 2.048mhz, or 1.544mhz clock must be applied at mclk. itu specification g.703 requires an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specifications require an accuracy of 32ppm for t1 interfaces. a prescaler divides the 16mhz, 8mhz, or 4mhz clock down to 2.048mhz. there is an on-board pll for the jitter attenuator, which converts the 2.048mhz clock to a 1.544mhz rate for t1 applications. setting jamux (tr.lic2.3) to a logic 0 bypasses this pll. 10.23 jitter attenuator the device contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits through the jabds bit (tr.lic1.2). the 128-bit mode is used in applications where large excursions of wander are expected. the 32-bit mode is used in delay-sensitive applications. the characteristics of the attenuation are shown in figure 10-12 . the jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the jas bit (tr.lic1.3). setting the dja bit (tr.lic1.1) disables (in effect, removes) the jitter attenuator. on-board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the tclkt pin to create a smooth jitter-free clock that is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/bursty clock at the tclkt pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120ui p-p (buffer depth is 128 bits) or 28ui p-p (buffer depth is 32 bits), then the transceiver divides the internal nominal 32.768mhz (e1) or 24.704mhz (t1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. when the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (jalt) bit in status register 1 (tr.sr1.4). 10.24 cmi (code mark inversion) option the device provides a cmi interface for connection to optic al transports. this interface is a unipolar 1t2b signal type. ones are encoded as either a logical 1 or 0 level for the full duration of the clock period. zeros are encoded as a 0-to-1 transition at the middle of the clock period. figure 10-6. cmi coding transmit and receive cmi are enabled through tr.lic4.7. when this register bit is set, the ttip pin outputs cmi- coded data at normal levels. this signal can be used to directly drive an optical interface. when cmi is enabled, the user can also use hdb3/b8zs coding. when this register bit is set, the rtip pin becomes a unipolar cmi input. the cmi signal is processed to extract and align the clock with data. 0 1 11 001 clock data cmi
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 104 of 338 10.25 recommended circuits figure 10-7. basic interface refer to application note 324: t1/e1 network interface design for more information on protected interfaces. table 10-13. transformer specifications specification recommended value turns ratio 3.3v applications 1:1 (receive) and 1:2 (transmit) 2% primary inductance 600  h (min) leakage inductance 1.0  h (max) intertwining capacitance 40pf (max) transmit transformer dc resistance primary (device side) secondary 1.0 ? (max) 2.0 ? (max) receive transformer dc resistance primary (device side) secondary 1.2 ? (max) 1.2 ? (max) ttip tring rtip rring dvdd tvdd rvdd vdd dvss tvss rvss DS33R11 r r 2:1 1:1 c 0.1f 0.1f 0.1f 0.01f transmit line receive line 0.1f 10f 10f + + note 1: all resistor values are 1%. note 2: resistors r should be set to 60  each if the internal receive-side termination feature is enabled. when this feature is disabled, r = 37.5  for 75  coaxial e1 lines, 60  for 120  twisted-pair e1 lines, or 50  for 100  twisted-pair t1 lines. note 3: c = 1  f ceramic.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 105 of 338 figure 10-8. e1 transmit pulse template figure 10-9. t1 transmit pulse template 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ? systems, 1.0 on the scale = 2.37vpeak in 120 ? systems, 1.0 on the scale = 3.00vpeak) g.703 template 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 time (ns) normalized amplitude t1.102/87, t1.403, cb 119 ( oct. 79 ) , and i.431 template -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui time amp. maximum curve ui time amp. minimum curve
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 106 of 338 figure 10-10. jitter tolerance figure 10-11. jitter tolerance (e1 mode) frequency (hz) unit intervals (ui p-p ) 1k 100 10 1 0.1 10 100 1k 10k 100k device tolerance 1 minimum tolerance level as per itu g.823 40 1.5 0.2 20 2.4k 18k frequency (hz) unit intervals (ui p-p ) 1k 100 10 1 0.1 10 100 1k 10k 100k device tolerance 1 tr 62411 (dec. 90) itu-t g.823
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 107 of 338 figure 10-12. jitter attenuation (t1 mode) figure 10-13. jitter attenuation (e1 mode) frequency (hz) 0 -20 -40 -60 1 10 100 1k 10k jitter attenuation (db) 100k itu g.7xx prohibited area tbr12 prohibited a rea e1 mode frequency (hz) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k tr 62411 (dec. 90) prohibited area c u r v e b c u rve a t1 mode
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 108 of 338 figure 10-14. optional crystal connections 10.26 t1/e1/j1 transceiver bert function the bert block can generate and detect pseudorandom and repeating bit patterns. it is used to test and stress data communication links, and it is capable of generating and detecting the following patterns:  the pseudorandom patterns 2e7, 2e11, 2e15, and qrss  a repetitive pattern from 1 to 32 bits in length  alternating (16-bit) words that flip every 1 to 256 words  daly pattern the bert receiver has a 32-bit bit counter and a 24-bit e rror counter. the bert receiver reports three events: a change in receive synchronizer status, a bit error being detected, and if either the bit counter or the error counter overflows. each of these events can be masked within the bert function through the bert control register 1 (tr.bc1). if the software detects that the bert has reported an event, then the software must read the bert information register (bir) to determine which event(s) has occurred. to activate the bert block, the host must configure the bert mux through the tr.bic register. 10.26.1 bert status tr.sr9 contains the status information on the bert function. the host can be alerted through this register when there is a bert change-of-state. a major change-of-state is defined as either a change in the receive synchronization (i.e., the bert has gone into or out of rece ive synchronization), a bit error has been detected, or an overflow has occurred in either the bit counter or the error counter. the host must read status register 9 (tr.sr9) to determine the change-of-state. 10.26.2 bert mapping the bert function can be assigned to the network direction or backplane direction through the direction control bit in the bic register (tr.bic.1). see figure 10-15 and figure 10-16 . the bert also can be assigned on a per- channel basis. the bert transmit control selector (btcs) and bert receive control selector (brcs) bits of the per-channel pointer register (tr.pcpr) are used to map the bert function into time slots of the transmit and receive data streams. in t1 mode, the user can enable m apping into the f-bit position for the transmit and receive directions through the rfus and tfus bits in the bert interface control (tr.bic) register. xtald c1 c2 1.544mhz/2.048mhz mclk note: c1 and c2 should be 5pf lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the device.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 109 of 338 figure 10-15. simplified diagram of bert in network direction figure 10-16. simplified diagram of bert in backplane direction bert transmitter bert receiver per-channel and f-bit (t1 mode) mapping 1 0 from receive framer to receive system backplane interface from transmit system backplane interface to transmit framer per-channel and f-bit (t1 mode) mapping bert transmitter bert receiver 1 0 from receive framer to receive system backplane interface from transmit system backplane interface to transmit framer
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 110 of 338 10.26.3 bert repetitive pattern set these registers must be properly loaded for the bert to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a daly pattern. for a repetitive pattern that is fewer than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. for example, if the pattern was the repeating 5-bit pattern ?01101? (where the rightmost bit is the one sent first and received first), then tr.brp1 should be loaded with adh, tr.brp2 with b5h, tr.brp 3 with d6h, and tr.brp4 with 5ah. for a pseudorandom pattern, all four registers should be loaded with all 1s (i.e., ffh). for an alternating word pattern, one word should be placed into tr.brp1 and tr.brp2 and the other word should be placed into tr.brp3 and tr.brp4. for example, if the dds stress pattern ?7e? is to be descri bed, the user would place 00h in tr.brp1, 00h in tr.brp2, 7eh in tr.brp3, and 7eh in tr.brp4 and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7eh to be sent and received. 10.26.4 bert bit counter the bert bit counter is comprised of tr.bbc1, tr. bbc2, tr.bbc3, and tr.bbc4. once bert has achieved synchronization, this 32-bit counter increments for each data bi t (i.e., clock) received. toggling the lc control bit in tr.bc1 can clear this counter. this counter saturates when full and sets the bbco status bit. 10.26.5 bert error counter the bert error counter is comprised of tr.bec1, tr.bec2, and tr.bec3. once bert has achieved synchronization, this 24-bit counter increments for each data bit received in error. toggling the lc control bit in tr.bc1 can clear this counter. this counter saturates when full and sets the beco status bit. 10.26.6 bert alternating word-count rate when the bert is programmed in the alternating word mode, each word repeats for the count loaded into tr.bawc. one word should be placed into tr.brp1 and tr.brp2 and the other word should be placed into tr.brp3 and tr.brp4.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 111 of 338 10.27 payload error-insertion function (t1 mode only) an error-insertion function is available in the transceiver and is used to create errors in the payload portion of the t1 frame in the transmit path. this function is only available in t1 mode. errors can be inserted over the entire frame or the user can select which channels are to be corrupted. errors are created by inverting the last bit in the count sequence. for example, if the error rate 1 in 16 is selected, the 16th bit is inverted. f-bits are excluded from the count and are never corrupted. error rate changes occur on frame boundaries. error-insertion options include continuous and absolute number with both options supporting selectable insertion rates. table 10-14. transmit error-insertion setup sequence step action 1 enter desired error rate in the tr.erc register. note: if tr.er3 through tr.er0 = 0, no errors are generated even if the constant error-insertion feature is enabled. 2a or 2b for constant error insertion, set ce = 1 (tr.erc.4). for a defined number of errors: ? set ce = 0 (tr.erc.4) ? load tr.noe1 and tr.noe2 with the number of errors to be inserted ? toggle wnoe (tr.erc.7) from 0 to 1 to begin error insertion 10.27.1 number-of-errors registers the number-of-error registers determine how many errors are generated. up to 1023 errors can be generated. the host loads the number of errors to be generated into the tr.noe1 and tr.noe2 registers. the host can also update the number of errors to be created by first loading the prescribed value into the tr.noe registers and then toggling the wnoe bit in the error-rate control registers. table 10-15. error insertion examples value write read 000h do not create any errors no errors left to be inserted 001h create a single error one error left to be inserted 002h create two errors two errors left to be inserted 3ffh create 1023 errors 1023 errors left to be inserted
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 112 of 338 10.28 programmable backplane clock synthesizer the transceiver contains an on-chip clock synthesizer that generates a user-selectable clock output on the bpclk pin, referenced to the recovered receive clock (rclko). the synthesizer uses a phase-locked loop to generate low-jitter clocks. common applications include generation of port and backplane system clocks. the tr.ccr2 register is used to enable (tr.ccr2.0) and select (tr.ccr2.1 and tr.ccr2.2) the clock frequency of the bpclk pin. 10.29 fractional t1/e1 support the transceiver can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a usart or lapd controller in fractional t1/e1 or isdn-pri applications. the receive and transmit paths have independent enables. channel formats supported include 56kbps and 64kbps. this is accomplished by assigning an alternate function to the rchclk and tchclk pins. setting tr.ccr3.0 = 1 causes the rchclk pin to output a gapped clock as defined by the receive fractional t1/e1 function of the tr.pcpr register. setting tr.ccr3.2 = 1 causes the tchclk pin to output a gapped clock as defined by the transmit fractional t1/e1 function of the tr.pcpr regi ster. tr.ccr3.1 and tr.ccr3.3 can be used to select between 64kbps and 56kbps operation. see section 10.2 for details about programming the per-channel function. in t1 mode no clock is generated at the f-bit position. when 56kbps mode is selected, the lsb clock in the channel is omitted. only the seven most significant bits of the channel have clocks.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 113 of 338 10.30 t1/e1/j1 transmit flow diagrams figure 10-17. t1/j1 transmit flow diagram escr.4 tese tser tsig hsie1-3 through pcpr tx estore off-chip connection rdata from t1_rcv_logic lbcr1.1 plb hdlc engine #1 thms1 h1tc.4 h1tcs1-3 h1ttsbs hdlc engine #2 thms2 h2tc.4 h2tcs1-3 h2ttsbs pclr1-3 t1 transmit flow diagram key - pin - selector - register hardware signaling estore mux payload loopback hdlc mux #1 hdlc mux #2 hdlc fdl #2 hdlc fdl #1 tdata teso tlink h1tc.4 thms1 fdl mux tfdl tx fdl zero stuffer h2tc.4 thms2 t1tcr2.5 tzse t1tcr1.2 tfdls tfdl boc engine boc mux bocc.0 sboc idle code mux idle code array tcice1-3 loop code gen loop code d4 12th fs yellow alarm fps or ft/fs insertion esf yellow alarm t1ccr1.2 tfm t1tcr2.2 td4ym t1tcr1.0 tyel per-channel loopback software sig software sig registers ssie1-3 f-bit mux tfpt t1tcr1.5 to fdl mux to esf yellow mux to fdl mux tloop t1ccr1.0
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 114 of 338 b8zs encoding bipolar/ nrz coding t1tcr2.7 b8zse iocr1.0 odf 1/2 clk/ full clk ccr1.4 odm tpos tneg fdl mux esf yellow from boc mux from f-bit mux from esf yellow alarm tfpt t1tcr1.5 tfm t1ccr1.2 tyel t1tcr1.0 crc mux tcpt t1tcr1.5 d4 bit 2 yellow alm bert engine bert mux f-bit corruption payload error insertion tfm t1ccr1.2 td4ym t1tcr2.2 tyel t1tcr1.0 tfus bic.3 f-bit btcs1-3 from pcpr berten bic.0 t1tcr2.3 fbct1 t1tcr2.4 fbct2 noel != 0 peics1-3 erc.4 ce bit 7 stuffing pulse density enforcer crc calculation ds0 monitor blue alarm b7se t1tcr2.0 ssie1-3 gb7s t1tcr1.3 tpdv info1.6 t1ccr1.1 pde tcm0-4 tds0sel.0 - .3 tdsom t1tcr1.1 tbl
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 115 of 338 figure 10-18. e1 transmit flow diagram tser tsig hsie1-4 through pcpr tx estore escr.4 tese teso tdata off-chip connection rdata from e1_rcv_logic lbcr1.1 plb hdlc engine #1 thms1 h1tc.4 h1tcs1-4 h1ttsbs t1sabe4- t1sabe8 thms1 h1tc.4 h1ttsbs.4 - h1ttsbs.0 hdlc engine #2 thms2 h2tc.4 h2tcs1-4 h2ttsbs t2sabe4-t2sabe8 thms2 h2tc.4 h2ttsbs.4 - h2ttsbs.0 btcs1-4 berten (bic.0) from pcpr bert engine to per-channel mux e1 transmit flow diagram key - pin - selector - register hardware signaling estore mux payload loopback mux hdlc ds0 mux #1 hdlc sa-bit mux #1 hdlc ds0 mux #2 bert mux hdlc sa-bit mux #2 idle code mux idle code array tcice1-4
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 116 of 338 per-channel loopback from idle code mux rdata from e1_rcv_logic pclr1-4 sa-bit mux tnaf thms1 thms2 h1tc.4 h2tc.4 ts0 mux taf/tnaf(non sa) si-bit mux e1tcr1.4 tsis auto e- bit gen tlink mux tlink auto ra gen tsacr mux sa4s - sa8s e1tcr2.2 aebe e1tcr2.5 - e1tcr2.7 e1tcr2.8 ara tsiaf tsinaf tra tsa4 tsa5 tsa6 tsa7 tsa8 tsacr software sig tsa1 e1tcr1.3 ts1-16 ssie1-4 e1tcr1.0 t16s si/crc4 mux e1tcr1.0 tcrc4 si = crc4 mf align word (does not overwrite e-bits) crc calculate crc re- calculate e1tcr1.0 tcrc4 ccr1.6 crc4r ds0 monitor tcm0-tcm4 tdsom auto ais gen ua1 gen e1tcr2.1 aais e1tcr1.5 tua1 hdb3 encoding e1tcr1.2 thdb3 to bipolar/nrz coding mux e1 transmit flow diagram tfpt e1tcr1.7 tds0sel.0 - tds0sel.4
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 117 of 338 11 device registers ten address lines are used to address the register space. table 11-1 shows the register map for the DS33R11. the addressable range for the device is 0000h to 08ffh. each register section is 64 bytes deep. global registers are preserved for software compatibility with multiport devices. the serial interface (line) registers are used to configure the serial port and the associated transport protocol. the ethernet interface (subscriber) registers are used to control and observe each of the ethernet ports. the registers associated with the mac must be configured through indirect register write /read access due to the architecture of the device. when writing to a register input va lues for unused bits and r egisters (those designated wi th ?-?) should be zero, as these bits and registers are reserved. when a register is read from, the values of the unused bits and registers should be ignored. a latched status bit is set when an event happens and is cleared when read. the register details are provided in the following tables. table 11-1. register address map mapper/ port chip select global registers arbiter bert serial interface ethernet interface t1/e1/j1 transceiver ethernet mapper cs =0, cst =1 0000h? 003fh 0040h? 007fh 0080h? 00bfh 00c0h? 013fh 0140h? 17fh ? t1/e1/j1 port 1 cs =1, cst =0 ? ? ? ? ? 000h?0ffh
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 118 of 338 11.1 register bit maps table 11-2 , table 11-3 , table 11-4 , table 11-5 , table 11-6 , and table 11-7 contain the registers of the DS33R11. bits that are reserved are noted with a single dash ?-?. all registers not lis ted are reserved and should be initialized with a value of 00h for proper operation, unless otherwise noted. 11.1.1 global ethernet mapper register bit map table 11-2. global ethernet mapper register bit map a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 00h gl.idrl id07 id06 id05 id04 id03 id02 id01 id00 01h gl.idrh id15 id14 id13 id12 id11 id10 id09 id08 02h gl.cr1 - - - - - ref_clko intm rst 03h gl.blr - - - - - - - gl.blc1 04h gl.rtcal - - - rlcals1 - - - tlcals1 05h gl.srcals - - - - - - refclks syscls 06h gl.lie - - - lin1tie - - - lin1rie 07h gl.lis - - - lin1tis - - - lin1ris 08h gl.sie - - - - - - - sub1ie 09h gl.sis - - - - - - - sub1is 0ah gl.trqie - - - tq1ie - - - rq1ie 0bh gl.trqis - - - tq1is - - - rq1is 0ch gl.bie - - - - - - - bie 0dh gl.bis - - - - - - - bis 0eh gl.con1 - - - - - - - line0 0fh reserved - - - - - - - - 10h reserved - - - - - - - - 11h reserved - - - - - - - - 12h gl.c1qpr - - - - c1mrpr c1hwpr c1mhpr c1hrpr 13h reserved - - - - - - - - 14h reserved - - - - - - - - 15h reserved - - - - - - - - 20h gl.bisten - - - - - - - biste 21h gl.bistpf - - - - - - bistdn bistpf note: 22h?3fh are reserved.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 119 of 338 11.1.2 arbiter register bit map table 11-3. arbiter register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 40h ar.rqsc1 rqsc7 rqsc6 rqsc5 rqsc4 rqsc3 rqsc2 rqsc1 rqsc0 41h ar.tqsc1 tqsc7 tqsc6 tqsc5 tqsc4 tqsc3 tqsc2 tqsc1 tqsc0 11.1.3 bert register bit map table 11-4. bert register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 080h bcr - pmu rnpl rpic mpr aprd tnpl tpic 081h reserved - - - - - - - - 082h bpclr - qrss pts plf4 plf3 plf2 plf1 plf0 083h bpchr - - - ptf4 ptf3 ptf2 ptf1 ptf0 084h bspb0r bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 085h bspb1r bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 086h bspb2r bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 087h bspb3r bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 088h teicr - - tier2 tier1 tier0 bei tsei - 08ah reserved - - - - - - - - 08bh reserved - - - - - - - - 08ch bsr - - - - pms - bec oos 08dh reserved - - - - - - - - 08eh bsrl - - - - pmsl bel becl oosl 08fh reserved - - - - - - - - 90h bsrie - - - - pmsie beie becie oosie 91h reserved - - - - - - - - 92h reserved - - - - - - - - 93h reserved - - - - - - - - 94h rbecb0r bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 95h rbecb1r bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 96h rbecb2r bec23 bec22 bec21 bec20 bec19 bec18 bec17 bec16 97h reserved - - - - - - - - 98h rbcb0 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 99h rbcb1 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 9ah rbcb2 bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 9bh rbcb3 bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 9ch reserved - - - - - - - - 9dh reserved - - - - - - - - 9eh reserved - - - - - - - - 9fh reserved - - - - - - - -
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 120 of 338 11.1.4 serial interface register bit map table 11-5. serial interface register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0c0h li.tslcr - - - - - - - tdenplt 0c1h li.rstpd - - - - - - reset - 0c2h li.lpbk - - - - - - - qlp 0c3h reserved - - - - - - - - 0c4h li.tppcl - - tfad tf16 tifv tsd tbre - 0c5h li.tifgc tifg7 tifg6 tifg 5 tifg4 tifg3 ti fg2 tifg1 tifg0 0c6h li.teplc tpen7 tpen6 tpen5 tpen4 tpen3 tpen2 tpen1 tpen0 0c7h li.tephc meims tper6 tper5 tper4 tper3 tper2 tper1 tper0 0c8h li.tppsr - - - - - - - tepf 0c9h li.tppsrl - - - - - - - tepfl 0cah li.tppsrie - - - - - - - tepfie 0cbh reserved - - - - - - - - 0cch li.tpcr0 tpc7 tpc6 tpc5 tpc4 tpc3 tpc2 tpc1 tpc0 0cdh li.tpcr1 tpc15 tpc14 tpc13 tpc12 tpc11 tpc10 tpc9 tpc8 0ceh li.tpcr2 tpc23 tpc22 tpc21 tpc20 tpc19 tpc18 tpc17 tpc16 0cfh reserved - - - - - - - - 0d0h li.tbcr0 tbc7 tbc6 tbc5 tbc4 tbc3 tbc2 tbc1 tbc0 0d1h li.tbcr1 tbc15 tbc14 tbc13 tbc12 tbc11 tbc10 tbc9 tbc8 0d2h li.tbcr2 tbc23 tbc22 tbc21 tbc20 tbc19 tbc18 tbc17 tbc16 0d3h li.tbcr3 tbc31 tbc30 tbc29 tbc28 tbc27 tbc26 tbc25 tbc24 0d4h li.tmei - - - - - - - tmei 0d5h reserved - - - - - - - - 0d6h li.thpmuu - - - - - - - tpmuu 0d7h li.thpmus - - - - - - - tpmus 0d8h li.tx86ede - - - - - - - x86ed 0d9h li.trx86a x86tra7 x86tra6 x86tra5 x86tra4 x86tra3 x86tra2 x86tra1 x86tra0 0dah li.trx8c x86trc7 x86trc6 x86trc5 x86trc4 x86trc3 x86trc2 x86trc1 x86trc0 0dbh li.trx86sapih trsapih7 trsapih6 trsapih5 trsapih4 trsapih3 trsapih2 trsapih1 trsapih0 0dch li.trx86sapil trsapil7 trsapil6 trsapil5 trsapil4 trsapil3 trsapil2 trsapil1 trsapil0 0ddh li.cir cire cir6 cir5 cir4 cir3 cir2 cir1 cir0 100h li.rslcr - - - - - - - rdenplt 101h li.rppcl - - rfpd rf16 rfed rdd rbre rcce 102h li.rmpscl rmx7 rmx6 rmx5 rmx4 rmx3 rmx2 rmx1 rmx0 103h li.rmpsch rmx15 rmx14 rmx13 rmx12 rmx11 rmx10 rmx9 rmx8 104h li.rppsr - - - - - repc rapc rspc 105h li.rppsrl repl rapl ripdl rspdl rlpdl repcl rapcl rspcl 106h li.rppsrie repie rapie ripdie rspdie rlpdie repcie rapcie rspcie 107h reserved 108h li.rpcb0 rpc7 rpc6 rpc5 rpc4 rpc3 rpc2 rpc1 rpc0 109h li.rpcb1 rpc15 rpc14 rpc13 rpc12 rpc11 rpc10 rpc09 rpc08 10ah li.rpcb2 rpc23 rpc22 rpc21 rpc20 rpc19 rpc18 rpc17 rpc16 10ch li.rfpcb0 rfpc7 rfpc6 rfpc5 rfpc4 rfpc3 rfpc2 rfpc1 rfpc0 10dh li.rfpcb1 rfpc15 rfpc14 rfpc13 rfpc12 rfpc11 rfpc10 rfpc9 rfpc8 10eh li.rfpcb2 rfpc23 rfpc22 rfpc21 rfpc20 rfpc19 rfpc18 rfpc17 rfpc16 10fh reserved 110h li.rapcb0 rapc7 rapc6 rapc5 rapc4 rapc3 rapc2 rapc1 rapc0 111h li.rapcb1 rapc15 rapc14 rapc13 rapc12 rapc11 rapc10 rapc9 rapc8 112h li.rapcb2 rapc23 rapc22 rapc21 rapc20 rapc19 rapc18 rapc17 rapc16 113h reserved - - - - - - - -
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 121 of 338 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 114h li.rspcb0 rspc7 rspc6 rspc5 rspc4 rspc3 rspc2 rspc1 rspc0 115h li.rspcb1 rspc15 rspc14 rspc13 rspc12 rspc11 rspc10 rspc9 rspc8 116h li.rspcb2 rspc23 rspc22 rspc21 rspc20 rspc19 rspc18 rspc17 rspc16 118h li.rbc0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 119h li.rbc1 rbc15 rbc14 rbc13 rbc12 rbc11 rbc10 rbc9 rbc8 11ah li.rbc2 rbc23 rbc22 rbc21 rbc20 rbc19 rbc18 rbc17 rbc16 11bh li.rbc3 rbc31 rbc30 rbc29 rbc28 rbc27 rbc26 rbc25 rbc24 11ch li.rac0 rebc7 rebc6 rebc5 rebc4 rebc3 rebc2 rebc1 rebc0 11dh li.rac1 rebc15 rebc14 rebc13 rebc12 rebc11 rebc10 rebc9 rebc8 11eh li.rac2 rebc23 rebc22 rebc21 rebc20 rebc19 rebc18 rebc17 rebc16 11fh li.rac3 rebc31 rebc30 rebc29 rebc28 rebc27 rebc26 rebc25 rebc24 120h li.rhpmuu - - - - - - - rpmuu 121h li.rhpmus - - - - - - - rpmuus 122h li.rx86s - - - - sapihne sapilne cne ane 123h li.rx86lsie - - - - sapine01im sapinefeim cne3lim ane4im 124h li.tqlt tqlt7 tqlt6 tqlt5 tqlt4 tqlt3 tqlt2 tqlt1 tqlt0 125h li.tqht tqht7 tqht6 tqht5 tqht4 tqht3 tqht2 tqht1 tqht0 126h li.tqtie - - - - tfovfie tqovfie tqhtie tqltie 127h li.tqctls - - - - tfovfls tqovfls tqhtls tqltls note: 0deh?0ffh, 128h?13fh are reserved.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 122 of 338 11.1.5 ethernet interface register bit map table 11-6. ethernet interface register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 140h su.macradl macra7 macra6 macra5 macra4 macra3 macra2 macra1 macra0 141h su.macradh macra15 macra14 macra13 macra12 macra11 macra10 macra09 macra08 142h su.macrd0 macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 143h su.macrd1 macrd15 macrd14 macrd13 macrd12 macrd11 macrd10 macrd9 macrd8 144h su.macrd2 macrd23 macrd22 macrd21 macrd20 macrd19 macrd18 macrd17 macrd16 145h su.macrd3 macrd31 macrd30 macrd29 macrd28 macrd27 macrd26 macrd25 macrd24 146h su.macwd0 macwd7 macwd6 macwd5 macwd4 macwd3 macwd2 macwd1 macwd0 147h su.macwd1 macwd15 macwd14 macwd13 macwd12 macwd11 macwd10 macwd09 macwd08 148h su.macwd2 macwd23 macwd22 macwd21 macwd20 macwd19 macwd18 macwd17 macwd16 149h su.macwd3 macd31 macd30 macd29 macd28 macd27 macd26 macd25 macd24 14ah su.macawl macaw 7 macaw 6 macaw 5 macaw4 macaw3 macaw2 macaw1 macaw0 14bh su.macawh macaw 15 macaw 14 macaw 13 macaw12 macaw11 macaw10 macaw9 macaw8 14ch su.macrwc - - - - - - mcrw mcs 14eh reserved - - - - - - - - 14fh su.lpbk - - - - - - - qlp 150h su.gcr - - - - crcs h10s atflow jame 151h su.tfrc - - - - ncfq tpdfcb tprhbc tprcb 152h su.tfsl ur ec lc ed loc noc - fabort 153h su.tfsh pr hbf cc3 cc2 cc1 cc0 lco def 154h su.rfsb0 fl7 fl6 fl5 fl4 fl3 fl2 fl1 fl0 155h su.rfsb1 rf wt fl13 fl12 fl11 fl10 fl9 fl8 156h su.rfsb2 - - crce db miie ft cs ftl 157h su.rfsb3 mf - - bf mcf uf cf le 158h su.rmfsrl rmps7 rmps6 rmps5 rmps4 rmps3 rmps2 rmps1 rmps0 159h su.rmfsrh rmps15 rmps14 rmps13 rmps12 rmps11 rmps10 rmps09 rmps08 15ah su.rqlt rqlt7 rqlt6 rqlt 5 rqlt4 rqlt3 rq lt2 rqlt1 rqlt0 15bh su.rqht rqht7 rqht6 rqht5 rqht4 rqht3 rqht2 rqht1 rqht0 15ch su.qrie - - - - rfovfie rqvfie rqltie rqhtie 15dh su.qcrls - - - - rfovfls rqovfls rqhtls rqltls 15eh su.rfrc - ucfr cfrr lerr crcerr dbr miier bfr note: 15fh?17fh are reserved.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 123 of 338 11.1.6 mac register bit map table 11-7. mac indirect register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0000h su.maccr 31:24 reserved reserved reserved hdb ps reserved reserved reserved 0001h 23:16 dro oml1 oml0 f reserved reserved reserved reserved 0002h 15:8 reserved reserved reserved lcc reserved drty reserved astp 0003h 7:0 bolmt1 bolmt0 dc reserved te re reserved reserved 0004h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0005h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0006h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0007h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0008h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0009h reserved reserved reserved reserved reserved reserved reserved reserved reserved 000ah reserved reserved reserved reserved reserved reserved reserved reserved reserved 000bh reserved reserved reserved reserved reserved reserved reserved reserved reserved 000ch reserved reserved reserved reserved reserved reserved reserved reserved reserved 000dh reserved reserved reserved reserved reserved reserved reserved reserved reserved 000eh reserved reserved reserved reserved reserved reserved reserved reserved reserved 000fh reserved reserved reserved reserved reserved reserved reserved reserved reserved 0010h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0011h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0012h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0013h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0014h su.macmiia 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 0015h 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 0016h 15:8 phya4 phya3 phya2 phya1 phya0 miia4 miia3 miia2 0017h 7:0 miia1 miia0 reserved reserved reserved reserved miiw miib 0018h su.macmiid 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 0019h 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 001ah 15:8 miid15 miid14 miid13 miid12 miid11 miid10 miid09 miid08 001bh 7:0 miid07 miid06 miid05 miid04 miid03 miid02 miid01 miid00 001ch su.macfcr 31:24 pt15 pt14 pt13 pt12 pt11 pt10 pt09 pt08 001dh 23:16 pt07 pt06 pt05 pt04 pt03 pt02 pt01 pt00 001eh 15:8 reserved reserved reserved reserved reserved reserved reserved reserved 001fh 7:0 reserved reserved reserved reserved reserved pcf fce fcb 100h su.mmcctrl 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 101h 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 102h 15:8 reserved reserved mxfrm10 mxfrm9 mxfrm8 mxfrm7 mxfrm6 mxfrm5 103h 7:0 mxfrm4 mxfrm3 mxfrm2 mxfrm1 mxfrm0 reserved reserved reserved 10ch reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 10dh reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 10eh reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 10fh reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 110h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 124 of 338 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 111h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 112h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 113h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 200h su.rxfrmctr 31:24 rxfrmc31 rxfrmc30 rxfrmc29 rxfrmc28 rxfrmc27 rxfrmc26 rxfrmc25 rxfrmc24 201h 23:16 rxfrmc23 rxfrmc22 rxfrmc21 rxfrmc20 rxfrmc19 rxfrmc18 rxfrmc17 rxfrmc16 202h 15:8 rxfrmc15 rxfrmc14 rxfrmc13 rxfrmc12 rxfrmc11 rxfrmc10 rxfrmc9 rxfrmc8 203h 7:0 rxfrmc7 rxfrmc6 rxfrmc5 rxfrmc4 rxfrmc3 rxfrmc2 rxfrmc1 rxfrmc0 204h su.rxfrmokctr 31:24 rxfrmok31 rxfrmok30 rxfrmok29 rxfrmok28 rxfrmok27 rxfrmok26 rxfrmok25 rxfrmok24 205h 23:16 rxfrmok23 rxfrmok22 rxfrmok21 rxfrmok20 rxfrmok19 rxfrmok18 rxfrmok17 rxfrmok16 206h 15:8 rxfrmok15 rxfrmok14 rxfrmok13 rxfrmok12 rxfrmok11 rxfrmok10 rxfrmok9 rxfrmok8 207h 7:0 rxfrmok7 rxfrmok6 rxfrmok5 rxfrmok4 rxfrmok3 rxfrmok2 rxfrmok1 rxfrmok0 300h su.txfrmctr txfrmc31 txfrmc30 txfrmc29 txfrmc28 txfrmc27 txfrmc26 txfrmc25 txfrmc24 301h 23:16 txfrmc23 txfrmc22 txfrmc21 txfrmc20 txfrmc19 txfrmc18 txfrmc17 txfrmc16 302h 15:8 txfrmc15 txfrmc14 txfrmc13 txfrmc12 txfrmc11 txfrmc10 txfrmc9 txfrmc8 303h 7:0 txfrmc7 txfrmc6 txfrmc5 txfrmc4 txfrmc3 txfrmc2 txfrmc1 txfrmc0 308h su.txbytesctr txbytec31 txbytec30 txbytec29 txbytec28 txbytec27 txbytec26 txbytec25 txbytec24 309h 23:16 txbytec23 txbytec22 txbytec21 txbytec20 txbytec19 txbytec18 txbytec17 txbytec16 30ah 15:8 txbytec15 txbytec14 txbytec13 txbytec12 txbytec11 txbytec10 txbytec9 txbytec8 30bh 7:0 txbytec7 txbytec6 txbytec5 txbytec4 txbytec3 txbytec2 txbytec1 txbytec0 30ch su.txbytesokctr txbyteok31 txbyteok30 txbyteok29 txbyteok28 txbyteok27 txbyteok26 txbyteok25 txbyteok24 30dh 23:16 txbyteok23 txbyteok22 txbyteok21 txbyteok20 txbyteok19 txbyteok18 txbyteok17 txbyteok16 30eh 15:8 txbyteok15 txbyteok14 txbyteok13 txbyteok12 txbyteok11 txbyteok10 txbyteok9 txbyteok8 30fh 7:0 txbyteok7 txbyteok6 txbyteok5 txbyteok4 txbyteok3 txbyteok2 txbyteok1 txbyteok0 334h su.txfrmundr txfrmu31 txfrmu30 txfrmu29 txfrmu28 txfrmu27 txfrmu26 txfrmu25 txfrmu24 335h 23:16 txfrmu23 txfrmu22 txfrmu21 txfrmu20 txfrmu19 txfrmu18 txfrmu17 txfrmu16 336h 15:8 txfrmu15 txfrmu14 txfrmu13 txfrmu12 txfrmu11 txfrmu10 txfrmu9 txfrmu8 337h 7:0 txfrmu7 txfrmu6 txfrmu5 txfrmu4 txfrmu3 txfrmu2 txfrmu1 txfrmu0 338h su.txbdfrmctr txfrmbd31 txfrmbd30 txfrmbd29 txfrmbd28 txfrmbd27 txfrmbd26 txfrmbd25 txfrmbd24 339h 23:16 txfrmbd23 txfrmbd22 txfrmbd21 txfrmbd20 txfrmbd19 txfrmbd18 txfrmbd17 txfrmbd16 33ah 15:8 txfrmbd15 txfrmbd14 txfrmbd13 txfrmbd12 txfrmbd11 txfrmbd10 txfrmbd9 txfrmbd8 33bh 7:0 txfrmbd7 txfrmbd6 txfrmbd5 txfrmbd4 txfrmbd3 txfrmbd2 txfrmbd1 txfrmbd0 note that the addresses in the tabl e above are the indirect addresses that must be provided to the su.macawh and su.macawl. all unused and reserved locations must be in itialized to zero for proper operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 125 of 338 table 11-8. t1/e1/j1 transceiver register bit map (active when cst = 0) a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 000h tr.mstrreg ? ? ? ? test1 test0 t1/e1 sftrst 001h tr.iocr1 rsms rsms2 rsms1 rsio tsdw tsm tsio odf 002h tr.iocr2 rdclkinv tdclkinv rsyncinv tsyncinv t ssyncinv h100en tsclkm rsclkm 003h tr.t1rcr1 ? arc oof1 oof2 syncc synct synce r esync 004h tr.t1rcr2 ? rfm rb8zs rslc96 rzse ? rjc rd4ym 005h tr.t1tcr1 tjc tfpt tcpt tsse gb7s tfdls tbl tyel 006h tr.t1tcr2 tb8zs tslc96 tzse fbct2 fbct1 td4ym reserved tb7zs 007h tr.t1ccr1 ? ? ? trai-ci tais-ci tfm pde tloop 008h tr.ssie1-t1 tr.ssie1-e1 ch8 ch7 ch7 ch6 ch6 ch5 ch5 ch4 ch4 ch3 ch3 ch2 ch2 ch1 ch1 ucaw 009h tr.ssie2-t1 tr.ssie2-e1 ch16 ch15 ch15 ch14 ch14 ch13 ch13 ch12 ch12 ch11 ch11 ch10 ch10 ch9 ch9 ch8 00ah tr.ssie3-t1 tr.ssie3-e1 ch24 ch22 ch23 ch21 ch22 ch20 ch21 ch19 ch20 ch18 ch19 ch17 ch18 ch16 ch17 lcaw 00bh tr.ssie4 ch30 ch29 ch28 ch27 ch26 ch25 ch24 ch23 00ch tr.t1rdmr1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 00dh tr.t1rdmr2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 00eh tr.t1rdmr3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 00fh tr.idr id7 id6 id5 id4 id3 id2 id1 id0 010h tr.info1 rpdv tpdv cofa 8zd 16zd sefe b8zs fbe 011h tr.info2 bsync bd tcle tocd rl3 rl2 rl1 rl0 012h tr.info3 ? ? ? ? ? crcrc fasrc casrc 013h reserved ? ? ? ? ? ? ? ? 014h tr.iir1 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 015h tr.iir2 ? ? ? ? ? ? ? sr9 016h tr.sr1 ilut timer rscos jalt lrcl tcle tocd lolitc 017h tr.imr1 ilut timer rscos jalt lrcl tcle tocd lolitc 018h tr.sr2 ryelc rua1c frclc rlosc ryel rua1 frcl rlos 019h tr.imr2 ryelc rua1c frclc rlosc ryel rua1 frcl rlos 01ah tr.sr3 lspare ldn lup lotc lorc v52lnk rdma rra 01bh tr.imr3 lspare ldn lup lotc lorc v52lnk rdma rra 01ch tr.sr4 rais-ci rsa1 rsa0 tmf taf rmf rcmf raf 01dh tr.imr4 rais-ci rsa1 rsa0 tmf taf rmf rcmf raf 01eh tr.sr5 ? ? tesf tesem tslip resf resem rslip 01fh tr.imr5 ? ? tesf tesem tslip resf resem rslip 020h tr.sr6 ? tmend rpe rps rhwm rne tlwm tnf 021h tr.imr6 ? tmend rpe rps rhwm rne tlwm tnf 022h tr.sr7 ? tmend rpe rps rhwm rne tlwm tnf 023h tr.imr7 ? tmend rpe rps rhwm rne tlwm tnf 024h tr.sr8 ? ? bocc rfdlad rfdlf tfdle rmtch rboc 025h tr.imr8 ? ? bocc rfdlad rfdlf tfdle rmtch rboc 026h tr.sr9 ? bbed bbco bec0 bra1 bra0 brlos bsync 027h tr.imr9 ? bbed bbco bec0 bra1 bra0 brlos bsync 028h tr.pcpr rsaoics rsrcs rfcs brcs thscs peics tfcs btcs 029h tr.pcdr1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 02ah tr.pcdr2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 02bh tr.pcdr3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 02ch tr.pcdr4 ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 02dh tr.info4 ? ? ? ? h2udr h2obt h1udr h1obt 02eh tr.info5 ? ? tempty tfull rempty ps2 ps1 ps0 02fh tr.info6 ? ? tempty tfull rempty ps2 ps1 ps0 030h tr.info7 csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa 031h tr.h1rc rhr rhms ? ? hdlcd ? ? rsfd
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 126 of 338 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 032h tr.h2rc rhr rhms ? ? hdlcd ? ? rsfd 033h tr.e1rcr1 rserc rsigm rhdb3 rg802 rcrc4 frc synce r esync 034h tr.e1rcr2 ? ? ? ? ? ? ? rcla 035h tr.e1tcr1 tfpt t16s tua1 tsis tsa1 thdb3 tg802 tcrc4 036h tr.e1tcr2 reserved reserved reserved reserved reserved aebe aais ara 037h tr.bocc ? ? ? rboce rbr rbf1 rbf0 sboc 038h tr.rsinfo1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 039h tr.rsinfo2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 03ah tr.rsinfo3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 03bh tr.rsinfo4 ? ? ch30 ch29 ch28 ch27 ch26 ch25 03ch tr.rscse1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 03dh tr.rscse2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 03eh tr.rscse3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 03fh tr.rscse4 ? ? ch30 ch29 ch28 ch27 ch26 ch25 040h tr.sigcr grsre ? ? rfe rff rccs tccs frsao 041h tr.ercnt ? mecu ecus eams vcrfs fsbe moscrf lcvcrf 042h tr.lcvcr1 lcvc15 lcvc14 lcvc13 lcvc12 lcvc11 lcvc10 lcvc9 lccv8 043h tr.lcvcr2 lcvc7 lcvc6 lcvc5 lcvc4 lcvc3 lcvc2 lcvc1 lcvc0 044h tr.pcvcr1 pcvc15 pcvc14 pcvc13 pcvc12 pcvc11 pcvc10 pcvc9 pcvc8 045h tr.pcvcr2 pcvc7 pcvc6 pcvc5 pcvc4 pcvc3 pcvc2 pcvc1 pcvc0 046h tr.foscr1 fos15 fos14 fos13 fos12 fos11 fos10 fos9 fos8 047h tr.foscr2 fos7 fos6 fos5 fos4 fos3 fo s2 fos1 fos0 048h tr.ebcr1 eb15 eb14 eb13 eb12 eb11 eb10 eb9 eb8 049h tr.ebcr2 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 04ah tr.lbcr lts ? ? liuc llb rlb plb flb 04bh tr.pclr1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 04ch tr.pclr2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 04dh tr.pclr3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 04eh tr.pclr4 ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 04fh tr.escr tesalgn tesr tesmdm tese resalgn resr resmdm rese 050h tr.ts1 transmit signaling bit format changes with operating mode. see re gister definition. 051h tr.ts2 transmit signaling bit format changes with operating mode. see re gister definition. 052h tr.ts3 transmit signaling bit format changes with operating mode. see re gister definition. 053h tr.ts4 transmit signaling bit format changes with operating mode. see re gister definition. 054h tr.ts5 transmit signaling bit format changes with operating mode. see re gister definition. 055h tr.ts6 transmit signaling bit format changes with operating mode. see re gister definition. 056h tr.ts7 transmit signaling bit format changes with operating mode. see re gister definition. 057h tr.ts8 transmit signaling bit format changes with operating mode. see re gister definition. 058h tr.ts9 transmit signaling bit format changes with operating mode. see re gister definition. 059h tr.ts10 transmit signaling bit format changes with operating mode. see re gister definition. 05ah tr.ts11 transmit signaling bit format changes with operating mode. see re gister definition. 05bh tr.ts12 transmit signaling bit format changes with operating mode. see re gister definition. 05ch tr.ts13 transmit signaling bit format changes with operating mode. see re gister definition. 05dh tr.ts14 transmit signaling bit format changes with operating mode. see re gister definition. 05eh tr.ts15 transmit signaling bit format changes with operating mode. see re gister definition. 05fh tr.ts16 transmit signaling bit format changes with operating mode. see re gister definition. 060h tr.rs1 receive signaling bit format changes with operating mode. see register definition. 061h tr.rs2 receive signaling bit format changes with operating mode. see register definition.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 127 of 338 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 062h tr.rs3 receive signaling bit format changes with operating mode. see register definition. 063h tr.rs4 receive signaling bit format changes with operating mode. see register definition. 064h tr.rs5 receive signaling bit format changes with operating mode. see register definition. 065h tr.rs6 receive signaling bit format changes with operating mode. see register definition. 066h tr.rs7 receive signaling bit format changes with operating mode. see register definition. 067h tr.rs8 receive signaling bit format changes with operating mode. see register definition. 068h tr.rs9 receive signaling bit format changes with operating mode. see register definition. 069h tr.rs10 receive signaling bit format changes with operating mode. see register definition. 06ah tr.rs11 receive signaling bit format changes with operating mode. see register definition. 06bh tr.rs12 receive signaling bit format changes with operating mode. see register definition. 06ch tr.rs13 receive signaling bit format changes with operating mode. see register definition. 06dh tr.rs14 receive signaling bit format changes with operating mode. see register definition. 06eh tr.rs15 receive signaling bit format changes with operating mode. see register definition. 06fh tr.rs16 receive signaling bit format changes with operating mode. see register definition. 070h tr.ccr1 ? crc4r sie odm ? tcss1 tcss0 rlosf 071h tr.ccr2 ? ? ? ? ? bpcs1 bpcs0 bpen 072h tr.ccr3 ? ? ? ? tdatfmt tgpcken rdatfmt rgpcken 073h tr.ccr4 rlt3 rlt2 rlt1 rlt0 uop3 uop2 uop1 uop0 074h tr.tds0sel ? ? ? tcm4 tcm3 tcm2 tcm1 tcm0 075h tr.tds0m b1 b2 b3 b4 b5 b6 b7 b8 076h tr.rds0sel ? ? ? rcm4 rcm3 rcm2 rcm1 rcm0 077h tr.rds0m b1 b2 b3 b4 b5 b6 b7 b8 078h tr.lic1 l2 l1 l0 egl jas jabds dja tpd 079h tr.lic2 ets lirst ibpv tua1 jamux ? scld clds 07ah tr.lic3 ? tces rces mm1 mm0 rsclke tsclke taoz 07bh tr.lic4 cmie cmii mps1 mps0 tt1 tt0 rt1 rt0 07ch reserved ? ? ? ? ? ? ? ? 07dh tr.tlbc ? agcd gc5 gc4 gc3 gc2 gc1 gc0 07eh tr.iaar gric gtic iaa5 iaa4 iaa3 iaa2 iaa1 iaa0 07fh tr.pcicr c7 c6 c5 c4 c3 c2 c1 c0 080h tr.tcice1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 081h tr.tcice2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 082h tr.tcice3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 083h tr.tcice4 ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 084h tr.rcice1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 085h tr.rcice2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 086h tr.rcice3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 087h tr.rcice4 ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 088h tr.rcbr1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 089h tr.rcbr2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 08ah tr.rcbr3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 08bh tr.rcbr4 ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 08ch tr.tcbr1 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 08dh tr.tcbr2 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 08eh tr.tcbr3 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 08fh tr.tcbr4 ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 090h tr.h1tc nofs teoml thr thms tfs teom tzsd tcrcd 091h tr.h1fc ? ? tflwm2 tflwm1 tflwm0 rfhwm2 rfhwm1 rfhwm0 092h tr.h1rcs1 rhcs8 rhcs7 rhcs6 rhcs5 rhcs4 rhcs3 rhcs2 rhcs1
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 128 of 338 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 093h tr.h1rcs2 rhcs16 rhcs15 rhcs14 rhcs13 rhcs12 rhcs11 rhcs10 rhcs9 094h tr.h1rcs3 rhcs24 rhcs23 rhcs22 rhcs21 rhcs20 rhcs19 rhcs18 rhcs17 095h tr.h1rcs4 rhcs32 rhcs31 rhcs30 rhcs29 rhcs28 rhcs27 rhcs26 rhcs25 096h tr.h1rtsbs rcb8se rcb7se rcb6se rcb5se rcb4se rcb3se rcb2se rcb1se 097h tr.h1tcs1 thcs8 thcs7 thcs6 thcs5 thcs4 thcs3 thcs2 thcs1 098h tr.h1tcs2 thcs16 thcs15 thcs14 thcs13 thcs12 thcs11 thcs10 thcs9 099h tr.h1tcs3 thcs24 thcs23 thcs22 thcs21 thcs20 thcs19 thcs18 thcs17 09ah tr.h1tcs4 thcs32 thcs31 thcs30 thcs29 thcs28 thcs27 thcs26 thcs25 09bh tr.h1ttsbs tcb8se tcb7se tcb6se tcb5se tcb4se tcb3se tcb2se tcb1se 09ch tr.h1rpba ms rpba6 rpba5 rpba4 rpba3 rpba2 rpba1 rpba0 09dh tr.h1tf thd7 thd6 thd5 thd4 thd3 thd2 thd1 thd0 09eh tr.h1rf rhd7 rhd6 rhd5 rhd4 rhd3 rhd2 rhd1 rhd0 09fh tr.h1tfba tfba7 tfba6 tfba5 tfba4 tfba3 tfba2 tfba1 tfba0 0a0h tr.h2tc nofs teoml thr thms tfs teom tzsd tcrcd 0a1h tr.h2fc ? ? tflwm2 tflwm1 tflwm0 rfhwm2 rfhwm1 rfhwm0 0a2h tr.h2rcs1 rhcs8 rhcs7 rhcs6 rhcs5 rhcs4 rhcs3 rhcs2 rhcs1 0a3h tr.h2rcs2 rhcs16 rhcs15 rhcs14 rhcs13 rhcs12 rhcs11 rhcs10 rhcs9 0a4h tr.h2rcs3 rhcs24 rhcs23 rhcs22 rhcs21 rhcs20 rhcs19 rhcs18 rhcs17 0a5h tr.h2rcs4 rhcs32 rhcs31 rhcs30 rhcs29 rhcs28 rhcs27 rhcs26 rhcs25 0a6h tr.h2rtsbs rcb8se rcb7se rcb6se rcb5se rcb4se rcb3se rcb2se rcb1se 0a7h tr.h2tcs1 thcs8 thcs7 thcs6 thcs5 thcs4 thcs3 thcs2 thcs1 0a8h tr.h2tcs2 thcs16 thcs15 thcs14 thcs13 thcs12 thcs11 thcs10 thcs9 0a9h tr.h2tcs3 thcs24 thcs23 thcs22 thcs21 thcs20 thcs19 thcs18 thcs17 0aah tr.h2tcs4 thcs32 thcs31 thcs30 thcs29 thcs28 thcs27 thcs26 thcs25 0abh tr.h2ttsbs tcb8se tcb7se tcb6se tcb5se tcb4se tcb3se tcb2se tcb1se 0ach tr.h2rpba ms rpba6 rpba5 rpba4 rpba3 rpba2 rpba1 rpba0 0adh tr.h2tf thd7 thd6 thd5 thd4 thd3 thd2 thd1 thd0 0aeh tr.h2rf rhd7 rhd6 rhd5 rhd4 rhd3 rhd2 rhd1 rhd0 0afh tr.h2tfba tfba7 tfba6 tfba5 tfba4 tfba3 tfba2 tfba1 tfba0 0b6h tr.ibcc tc1 tc0 rup2 rup1 rup0 rdn2 rdn1 rdn0 0b7h tr.tcd1 c7 c6 c5 c4 c3 c2 c1 c0 0b8h tr.tcd2 c7 c6 c5 c4 c3 c2 c1 c0 0b9h tr.rupcd1 c7 c6 c5 c4 c3 c2 c1 c0 0bah tr.rupcd2 c7 c6 c5 c4 c3 c2 c1 c0 0bbh tr.rdncd1 c7 c6 c5 c4 c3 c2 c1 c0 0bch tr.rdncd2 c7 c6 c5 c4 c3 c2 c1 c0 0bdh tr.rscc ? ? ? ? ? rsc2 rsc1 rsc0 0beh tr.rscd1 c7 c6 c5 c4 c3 c2 c1 c0 0bfh tr.rscd2 c7 c6 c5 c4 c3 c2 c1 c0 0c0h tr.rfdl bit definitions change with bocc setting. see regi ster definition. 0c1h tr.tfdl tfdl7 tfdl6 tfdl5 tfdl4 tfdl3 tfdl2 tfdl1 tfdl0 0c2h tr.rfdlm1 rfdlm7 rfdlm6 rfdlm5 rfdlm4 rfdlm3 rfdlm2 rfdlm1 rfdlm0 0c3h tr.rfdlm2 rfdlm7 rfdlm6 rfdlm5 rfdlm4 rfdlm3 rfdlm2 rfdlm1 rfdlm0 0c3h reserved ? ? ? ? ? ? ? ? 0c5h reserved ? ? ? ? ? ? ? ? 0c6h tr.raf si 0 0 1 1 0 1 1 0c7h tr.rnaf si 1 a sa4 sa5 sa6 sa7 sa8 0c8h tr.rsiaf sif0 sif2 sif4 sif6 sif8 sif10 sif12 sif14 0c9h tr.rsinaf sif1 sif3 sif5 sif7 sif9 sif11 sif13 sif15 0cah tr.rra rraf1 rraf3 rraf5 rraf7 rraf9 rraf11 rraf13 rraf15 0cbh tr.rsa4 rsa4f1 rsa4f3 rsa4f5 rsa4f7 rsa4f9 rsa4f11 rsa4f13 rsa4f15 0cch tr.rsa5 rsa5f1 rsa5f3 rsa5f5 rsa5f7 rsa5f9 rsa5f11 rsa5f13 rsa5f15 0cdh tr.rsa6 rsa6f1 rsa6f3 rsa6f5 rsa6f7 rsa6f9 rsa6f11 rsa6f13 rsa6f15 0ceh tr.rsa7 rsa7f1 rsa7f3 rsa7f5 rsa7f7 rsa7f9 rsa7f11 rsa7f13 rsa7f15
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 129 of 338 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0cfh tr.rsa8 rsa8f1 rsa8f3 rsa8f5 rsa8f7 rsa8f9 rsa8f11 rsa8f13 rsa8f15 0d0h tr.taf si 0 0 1 1 0 1 1 0d1h tr.tnaf si 1 a sa4 sa5 sa6 sa7 sa8 0d2h tr.tsiaf tsif0 tsif2 tsif4 tsif6 tsif8 tsif10 tsif12 tsif14 0d3h tr.tsinaf tsif1 tsif3 tsif5 tsif7 tsif9 tsif11 tsif13 tsif15 0d4h tr.tra traf1 traf3 traf5 traf7 traf9 traf11 traf13 traf15 0d5h tr.tsa4 tsa4f1 tsa4f3 tsa4f5 tsa4f7 tsa4f9 tsa4f11 tsa4f13 tsa4f15 0d6h tr.tsa5 tsa5f1 tsa5f3 tsa5f5 tsa5f7 tsa5f9 tsa5f11 tsa5f13 tsa5f15 0d7h tr.tsa6 tsa6f1 tsa6f3 tsa6f5 tsa6f7 tsa6f9 tsa6f11 tsa6f13 tsa6f15 0d8h tr.tsa7 tsa7f1 tsa7f3 tsa7f5 tsa7f7 tsa7f9 tsa7f11 tsa7f13 tsa7f15 0d9h tr.tsa8 tsa8f1 tsa8f3 tsa8f5 tsa8f7 tsa8f9 tsa8f11 tsa8f13 tsa8f15 0dah tr.tsacr siaf sinaf ra sa4 sa5 sa6 sa7 sa8 0dbh tr.bawc acnt7 acnt6 acnt5 acnt4 acnt3 acnt2 acnt1 acnt0 0dch tr.brp1 rpat7 rpat6 rpat5 rpat4 rpat3 rpat2 rpat1 rpat0 0ddh tr.brp2 rpat15 rpat14 rpat13 rpat12 rpat11 rpat10 rpat9 rpat8 0deh tr.brp3 rpat23 rpat22 rpat21 rpat20 rpat19 rpat18 rpat17 rpat16 0dfh tr.brp4 rpat31 rpat30 rpat29 rpat28 rpat27 rpat26 rpat25 rpat24 0e0h tr.bc1 tc tinv rinv ps2 ps1 ps0 lc resync 0e1h tr.bc2 eib2 eib1 eib0 sbe rpl3 rpl2 rpl1 rpl0 0e2h reserved ? ? ? ? ? ? ? ? 0e3h tr.bbc1 bbc7 bbc6 bbc5 bbc4 bbc3 bbc2 bbc1 bbc0 0e4h tr.bbc2 bbc15 bbc14 bbc13 bbc12 bbc11 bbc10 bbc9 bbc8 0e5h tr.bbc3 bbc23 bbc22 bbc21 bbc20 bbc19 bbc18 bbc17 bbc16 0e6h tr.bbc4 bbc31 bbc30 bbc29 bbc28 bbc27 bbc26 bbc25 bbc24 0e7h tr.bec1 ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 0e8h tr.bec2 ec15 ec14 ec13 ec12 ec11 ec10 ec9 ec8 0e9h tr.bec3 ec23 ec22 ec21 ec20 ec19 ec18 ec17 ec16 0eah tr.bic ? rfus ? tbat tfus ? bertdir berten 0ebh tr.erc wnoe ? ? ce er3 er2 er1 er0 0ech tr.noe1 c7 c6 c5 c4 c3 c2 c1 c0 0edh tr.noe2 ? ? ? ? ? ? c9 c8 0eeh tr.noel1 c7 c6 c5 c4 c3 c2 c1 c0 0efh tr.noel2 ? ? ? ? ? ? c9 c8
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 130 of 338 11.2 global register defini tions for ethernet mapper functions contained in the global registers include: fram er reset, liu reset, device id, and bert interrupt status. these registers are preserved to provide code compatibility with the multiport devices in this product family. the global registers bit descriptions are presented below. register name: gl.idrl register description: global id low register register address: 00h bit # 7 6 5 4 3 2 1 0 name id07 id06 id05 id04 id03 id02 id01 id00 default 0 0 1 1 0 0 0 0 bit 7: id07 reserved for future use bit 6: id06 reserved for future use bit 5: id05 if this bit is set the device contains a rmii interface bit 4: id04 if this bit is set the device contains a mii interface bit 3: id03 if this bit is set the device contains an ethernet phy bits 0-2: id00-id02 a three-bit count that is equal to 000b for the first die revision, and is incremented with each successive die revision. may not match the two-letter die revision code on the top brand of the device. register name: gl.idrh register description: global id high register register address: 01h bit # 7 6 5 4 3 2 1 0 name id15 id14 id13 id12 id11 id10 id09 id08 default 0 0 0 0 0 0 1 0 bits 5-7: id13-15 number of ethernet ports in the device minus 1. (i.e. 000 = 1 ethernet port) bit 4: id12 if this bit is set the device has liu functionality bit 3: id11 if this bit is set the device has a framer bit 2: id10 reserved for future use bit 1: id09 if this bit is set the device has hdlc or x.86 encapsulation bit 0: id08 if this bit is set the device has inverse multiplexing functionality
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 131 of 338 register name: gl.cr1 register description: global control register 1 register address: 02h bit # 7 6 5 4 3 2 1 0 name - - - - - ref_clko intm rst default 0 0 0 bit 2: ref_clko off (ref_clko) this bit determines if the ref_clko is turned off 1 = ref_clko is disabled and outputs an active low signal. 0 = ref_clko is active and in accordance with rmii/mii selection bit 1: int pin mode (intm) this bit determines the inactive mode of the int pin. the int pin always drives low when active. 1 = pin is high impedance when not active 0 = pin drives high when not active bit 0: reset (rst). when this bit is set to 1, all of the internal data path and status and control registers (except this rst bit), on all ports, are reset to their default st ate. this bit must be set high for a minimum of 100ns. 0 = normal operation 1 = reset and force all internal registers to their default values register name: gl.blr register description: global bert connect register register address: 03h bit # 7 6 5 4 3 2 1 0 name - - - - - - - blc1 default 0 0 0 0 0 0 0 0 bit 0: bert connect 1 (blc1) if this bit is set to 1, the bert is connected to serial interface 1. the bert transmitter is connected to the transmit serial port and receive to receive serial port. when the bert is connected, normal data transfer is interrupted. note that connecting the bert overrides a connection to the serial interface, if a connection exists. when the bert is disconnected, the connection is restored.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 132 of 338 register name: gl.rtcal register description: global receive and transmit serial port clock activity latched status register address: 04h bit # 7 6 5 4 3 2 1 0 name - - - rlcals1 - - - tlcals1 default - - - - - - - - bit 4: receive serial interface clock activity latched status 1 (rlcals1) this bit is set to 1 if the receive clock for serial interface 1 has activity. this bit is cleared upon read. bit 0: transmit serial interface clock activity latched status 1 (tscals1) this bit is set to 1 if the transmit clock for serial interface 1 has activity. this bit is cleared upon read. register name: gl.srcals register description: global sdram reference clock activity latched status register address: 05h bit # 7 6 5 4 3 2 1 0 name - - - - - - refclks syscls default - - - - - - - - bit 1: reference clock activity latched status (refclks) this bit is set to 1 if ref_clk has activity. this bit is cleared upon read. bit 0: system clock input latched status (syscls) this bit is set to 1 if sysclki has activity. this bit is cleared upon read. register name: gl.lie register description: global serial interface interrupt enable register address: 06h bit # 7 6 5 4 3 2 1 0 name - - - lin1tie - - - lin1rie default 0 0 0 0 0 0 0 0 bit 4: serial interface 1 tx interrupt enable (line1tie) setting this bit to 1 enables an interrupt on lin1tis bit 0: serial interface 1 rx interrupt enable (line1rie) setting this bit to 1 enables an interrupt on lin1ris
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 133 of 338 register name: gl.lis register description: global serial interface interrupt status register address: 07h bit # 7 6 5 4 3 2 1 0 name - - - lin1tis - - - lin1ris default 0 0 0 0 0 0 0 0 bit 4: serial interface 1 tx interrupt status (line1tis) this bit is set if serial interface 1 transmit has an enabled interrupt generating event. serial interface interrupts consist of hdlc interrupts and x.86 interrupts. bit 0: serial interface 1 rx interrupt status (liner1is) this bit is set if serial interface 1 receive has an enabled interrupt generating event. serial interface interrupts consist of hdlc interrupts and x.86 interrupts. register name: gl.sie register description: global ethernet interface interrupt enable register address: 08h bit # 7 6 5 4 3 2 1 0 name - - - - - - - sub1ie default 0 0 0 0 0 0 0 0 bit 0: ethernet interface 1 interrupt enable (sub1ie) setting this bit to 1 enables an interrupt on sub1s. register name: gl.sis register description: global ethernet interface interrupt status register address: 09h bit # 7 6 5 4 3 2 1 0 name - - - - - - - sub1is default 0 0 0 0 0 0 0 0 bit 0: ethernet interface 1 interrupt status (sub1is) this bit is set to 1 if ethernet interface 1 has an enabled interrupt generating event. the ethernet interface consists of the mac and the rmii/mii port.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 134 of 338 register name: gl.trqie register description: global transmit receive queue interrupt enable register address: 0ah bit # 7 6 5 4 3 2 1 0 name - - - tq1ie - - - rq1ie default 0 0 0 0 0 0 0 0 bit 4: transmit queue 1 interrupt enable (tq1ie) setting this bit to 1 enables an interrupt on tq1is. bit 0: receive queue 1 interrupt enable (rq1ie) setting this bit to 1 enables an interrupt on rq1is. register name: gl.trqis register description: global transmit receive queue interrupt status register address: 0bh bit # 7 6 5 4 3 2 1 0 name - - - tq1is - - - rq1is default 0 0 0 0 0 0 0 0 bit 4: transmit queue 1 interrupt enable (tq1is) if this bit is set to 1, the transmit queue 1 has interrupt status event. transmit queue events are transmit queue crossing thresholds and queue overflows. bit 0: receive queue 1 interrupt status (rq1is) if this bit is set to 1, the receive queue 1 has interrupt status event. receive queue events are transmit queue crossing thresholds and queue overflows. register name: gl.bie register description: global bert interrupt enable register address: 0ch bit # 7 6 5 4 3 2 1 0 name - - - - - - - bie default 0 0 0 0 0 0 0 0 bit 0: bert interr upt enable (bie) setting this bit to 1 enables an interrupt on bis.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 135 of 338 register name: gl.bis register description: global bert interrupt status register address: 0dh bit # 7 6 5 4 3 2 1 0 name - - - - - - - bis default 0 0 0 0 0 0 0 0 bit 0: bert interr upt status (bis) this bit is set to 1 if the bert has an enabled interrupt generating event. register name: gl.con1 register description: connection register for ethernet interface 1 register address: 0eh bit # 7 6 5 4 3 2 1 0 name - - - - - - - line1[0] default 0 0 0 0 0 0 0 1 bit 0: line1[0] this bit is preserved to provide software com patibility with multiport devices. the line1[0] bit selects the ethernet port that is to be connected to the serial interface. note that bidirectional connection is assumed between the serial and ethernet interfaces. the connection register and corresponding queue size must be defined for proper operation. writing a 0 to this r egister will disconnect the connection. when a connection is disconnected, ?1?s are sourced to the serial interface transmit and to the hdlc receiver and the clocks to the hdlc transmitter/receiver are disabled.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 136 of 338 register name: gl.c1qpr register description: connection 1 queue pointer reset register address: 12h bit # 7 6 5 4 3 2 1 0 name - - - - c1mrpr c1hwpr c1mhpr c1hrpr default 0 0 0 0 0 0 0 0 bit 3: mac read pointer reset (c1mrpr) setting this bit to 1 resets the receive queue read pointer for connection 1. this queue pointer must be reset after a disconnect and before a connection. the user must clear the bit before subsequent reset operations. bit 2: hdlc write pointer reset (c1hwpr) setting this bit to 1 resets the receive queue write pointer for connection 1. this queue pointer must be reset after a disconnect and before a connection. the user must clear the bit before subsequent reset operations. bit 1: hdlc read pointer reset (c1mhpr) setting this bit to 1 resets the transmit queue read pointer for connection 1. this queue pointer must be reset after a disconnect and before a connection. the user must clear the bit before subsequent reset operations. bit 0: mac transmit write pointer reset (c1hrpr) setting this bit to 1 resets the transmit queue write pointer for connection 1. this queue pointer must be reset after a disconnect and before a connection. the user must clear the bit before subsequent reset operations. register name: gl.bisten register description: bist enable register address: 20h bit # 7 6 5 4 3 2 1 0 name - - - - - - - biste default 0 0 0 0 0 0 0 0 bit 0: bist enable (biste) if this bit is set the DS33R11 performs bist test on the sdram. normal data communication is halted while bist enable is high. the user must reset the DS33R11 after completion of bist test before normal dataflow can begin.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 137 of 338 register name: gl.bistpf register description: bist pass-fail register address: 21h bit # 7 6 5 4 3 2 1 0 name - - - - - - bistdn bistpf default 0 0 0 0 0 0 0 0 bit 1: bist done (bistdn) if this bit is set to 1, the DS33R11 has completed the bist test initiated by biste. the pass fail result is available in bistpf. bit 0: bist pass-fail (bistpf) this bit is equal to 0 after the DS33R11 performs bist testing on the sdram and the test passes. this bit is set to 1 if the test failed. this bit is valid only after the bist test is complete and the bist dn bit is set. if set this bit can only be cleared by resetting the DS33R11. register name: gl.sdmode1 register description: global sdram mode register 1 register address: 3ah bit # 7 6 5 4 3 2 1 0 name - - - - wt bl2 bl1 bl0 default 0 0 0 0 0 0 1 1 bit 3: wrap type (wt) this bit is used to configure the wrap mode. 0 = sequential 1 = interleave bits 0- 2: burst length 0 through 2 (bl0 ? bl2) these bits are used to determine the burst length. note: this register has a nonzero default value. this should be taken into consid eration when initializing the device. note: after changing the value of this register, the user must toggle the gl.sdmodews.sdmw bit to write the new values to the sdram.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 138 of 338 register name: gl.sdmode2 register description: global sdram mode register 2 register address: 3bh bit # 7 6 5 4 3 2 1 0 name - - - - - ltmod2 ltmod1 ltmod0 default 0 0 0 0 0 0 1 0 bits 0 - 2: cas latency mode (ltmod0 - ltmod2) these bits are used to setup cas latency note: only cas latency of 2 or 3 is allowed note: this register has a nonzero default value. this should be taken into consid eration when initializing the device. note: after changing the value of this register, the user must toggle the gl.sdmodews.sdmw bit to write the new values to the sdram. register name: gl.sdmodews register description: global sdram mode register write status register address: 3ch bit # 7 6 5 4 3 2 1 0 name - - - - - - - sdmw default 0 0 0 0 0 0 0 0 bit 0: sdram mode write (sdmw) setting this bit to 1 will write the current values of the mode control and refresh time control registers to the sdram. the user must clear this bit and set it again for subsequent write operations. register name: gl.sdrftc register description global sdram refresh time control register address: 3dh bit # 7 6 5 4 3 2 1 0 name sreft7 sreft6 sreft5 sreft4 sreft3 sreft2 sreft1 sreft0 default 0 1 0 0 0 1 1 0 bits 0 - 7: sdram refresh time control (sreft0 ? sreft7) these 8 bits are used to control the sdram refresh frequency. the refresh rate will be equal to this register value x 8 x 100mhz. note: this register has a nonzero default value. this should be taken into consid eration when initializing the device. note: after changing the value of this register, the user must toggle the gl.sdmodews.sdmw bit to write the new values to the sdram.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 139 of 338 11.3 arbiter registers the arbiter manages the transport between the ethernet port and the serial interface. it is responsible for queuing and dequeuing data to an external sdram. the arbiter handl es requests from the hdlc and mac to transfer data to/from the sdram. the base address of the arbiter register space is 0040h. 11.3.1 arbiter register bit descriptions register name: ar.rqsc1 register description: arbiter receive queue size connection register address: 40h bit # 7 6 5 4 3 2 1 0 name rqsc7 rqsc6 rqsc5 rqsc4 rqsc3 rqsc2 rqsc1 rqsc0 default 0 0 1 1 1 1 0 1 bits 0-7: receive queue size (rqsc[0:7]) these 7 bits of the size of receive queue associated with the connection. receive queue is for data arriving from the mac to be sent to the wan. the queue address size is defined in increments of 32 x 2048 bytes. the queue size is ar.rqsc1 multiplied by 32 to determine the number of 2048 byte packets that can be stored in the queue. this queue is constructed in the external sdram . note: queue size of 0 is not allowed and should never be set. register name: ar.tqsc1 register description: arbiter transmit queue size connection 1 register address: 41h bit # 7 6 5 4 3 2 1 0 name tqsc7 tqsc6 tqsc5 tqsc4 tqsc3 tqsc2 tqsc1 tqsc0 default 0 0 0 0 0 0 1 1 bits 0-7: transmit queue size (tqsc[0:7]) this is size of transmit queue associated with the connection. the queue address size is defined in increments of 32 packets. the range of bytes will depend on the external sdram connected to the DS33R11. transmit queue is the data queue for data arriving on the wan that is sent to the mac. note that queue size of 0 is not allowed and should never be set.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 140 of 338 11.4 bert registers register name: bcr register description: bert control register register address: 80h bit # 7 6 5 4 3 2 1 0 name - pmu rnpl rpic mpr aprd tnpl tpic default 0 0 0 0 0 0 0 0 bit 7: this bit must be kept low for proper operation. bit 6: performance monitoring update (pmu) this bit causes a performance monitoring update to be initiated. a 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). for a second performance monitoring update to be initiated, this bit must be set to 0, and back to 1. if pmu goes low before the pms bit goes high, an update might not be performed. bit 5: receive new pattern load (rnpl) a zero to one transition of this bit will cause the programmed test pattern (qrss, pts, plf [4:0}, ptf [4:0], and bsp [31:0]) to be loaded in to the receive pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. loading a new pattern will forces the receive pattern generator out of the ?sync? state which causes a resynchronization to be initiated. note: qrss, pts, plf [4:0}, ptf [4:0], and bsp [31:0] must not change from the time this bit transitions from 0 to 1 until four rclki clock cycles after this bit transitions from 0 to 1. bit 4: receive pattern inversion control (rpic) when 0, the receive incoming data stream is not altered. when 1, the receive incoming data stream is inverted. bit 3: manual pattern resynchronization (mpr) a zero to one transition of this bit will cause the receive pattern generator to resynchronize to the incoming pattern. this bit must be changed to zero and back to one for another resynchronization to be initiated. note: a manual resynchronization forces the receive pattern generator out of the ?sync? state. bit 2: automatic pattern resynchronization disable (aprd) when 0, the receive pattern generator will automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the incoming data stream bit and the receive pattern generator output bit did not match. when 1, the receive pattern generator will not automatically resynchronize to the incoming pattern. note: automatic synchronization is prevented by not allowing the receive pattern generator to automatically exit the ?sync? state. bit 1: transmit new pattern load (tnpl) a zero to one transition of this bit will cause the programmed test pattern (qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0]) to be loaded in to the transmit pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. note: qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0] must not change from the time this bit transitions from 0 to 1 until four tclke clock cycles after this bit transitions from 0 to 1. bit 0: transmit pattern inversion control (tpic) when 0, the transmit outgoing data stream is not altered. when 1, the transmit outgoing data stream is inverted.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 141 of 338 register name: bpclr register description: bert pattern configuration low register register address: 82h bit # 7 6 5 4 3 2 1 0 name - qrss pts plf4 plf3 plf2 plf1 plf0 default 0 0 0 0 0 0 0 0 bit 6: qrss enable (qrss) when 0, the pattern generator configuration is controlled by pts, plf[0:4], and ptf[0:4], and bsp[0:31]. when 1, the pattern generator configuration is forced to a qrss pattern with a generating polynomial of x 20 + x 17 + 1. the output of the pattern generator is forced to one if the next fourteen output bits are all zero. bit 5: pattern type select (pts) when 0, the pattern is a prbs pattern. when 1, the pattern is a repetitive pattern. register name: bpchr register description: bert pattern configuration high register register address: 83h bit # 7 6 5 4 3 2 1 0 name - - - ptf4 ptf3 ptf2 ptf1 ptf0 default 0 0 0 0 0 0 0 0 bits 4 to 0: pattern tap feedback (ptf[4:0]) these five bits control the prbs ?tap? feedback of the pattern generator. the ?tap? feedback is from bit y of the pattern generator (y = ptf[4:0] +1). these bits are ignored when programmed for a repetitive pattern. for a prbs signal, the feedback is an xor of bit n and bit y. the values possible are outlined in section 9.16 .
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 142 of 338 register name: bspb0r register description: bert pattern byte0 register register address: 84h bit # 7 6 5 4 3 2 1 0 name bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 default 0 0 0 0 0 0 0 0 bits 0 to 7: bert pattern (bsp[7:0]) lower eight bits of 32 bits. register description follows next register. register name: bspb1r register description: bert pattern byte 1 register register address: 85h bit # 7 6 5 4 3 2 1 0 name bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 default 0 0 0 0 0 0 0 0 bits 0 to 7: bert pattern (bsp[15:8]) 8 bits of 32 bits. register description below. register name: bspb2r register description: bert pattern byte2 register register address: 86h bit # 7 6 5 4 3 2 1 0 name bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 default 0 0 0 0 0 0 0 0 bits 0 to 7: bert pattern (bsp[23:16]) 8 bits of 32 bits. register description below. register name: bspb3r register description: bert seed/pattern byte3 register register address: 87h bit # 7 6 5 4 3 2 1 0 name bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 default 0 0 0 0 0 0 0 0 bits 0 to 8: bert pattern (bsp[31:24]) upper 8 bits of 32 bits. register description below. bert pattern (bsp[31:0]) these 32 bits are the programmable seed for a transmit prbs pattern, or the programmable pattern for a transmit or receive repetitive pattern. bsp(31) is the first bit output on the transmit side for a 32-bit repetitive pattern or 32-bit length prbs. bsp(31) is the first bit input on the receive side for a 32-bit repetitive pattern.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 143 of 338 register name: teicr register description: transmit error insertion control register register address: 88h bit # 7 6 5 4 3 2 1 0 name - - tier2 tier1 tier0 bei tsei - default 0 0 0 0 0 0 0 0 bits 3 ? 5: transmit error insertion rate (teir[2:0]) these three bits indicate the rate at which errors are inserted in the output data stream. one out of every 10 n bits is inverted. teir[2:0] is the value n. a teir[2:0] value of 0 disables error insertion at a specific rate. a teir[2:0] value of 1 result in every 10 th bit being inverted. a teir[2:0] value of 2 results in every 100 th bit being inverted. error insertion starts when this register is written to with a teir[2:0] value that is nonzero. if this register is written to during the middle of an error insertion process, the new error rate is started after the next error is inserted. bit 2: bit error insertion enable (bei) when 0, single bit error insertion is disabled. when 1, single bit error insertion is enabled. bit 1: transmit single error insert (tsei) this bit causes a bit error to be inserted in the transmit data stream if and single bit error insertion is enabled. a 0 to 1 transition causes a single bit error to be inserted. for a second bit error to be inserted, this bit must be set to 0, and back to 1. note: if this bit transitions more than once between error insertion opportunities, only one error is inserted. all other bits in this register besides bei and tsei and tier must be reset to 0 for proper operation. register name: bsr register description: bert status register register address: 8ch bit # 7 6 5 4 3 2 1 0 name - - - - pms - bec oos default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status (pms) this bit indicates the status of the receive performance monitoring register (counters) update. this bit will transition from low to high when the update is completed. pms is asynchronously forced low when the pmu bit goes low. tclke and rclki must be present. bit 1: bit error count (bec) when 0, the bit error count is zero. when 1, the bit error count is one or more. bit 0: out of synchronization (oos) when 0, the receive pattern generator is synchronized to the incoming pattern. when 1, the receive pattern generator is not synchronized to the incoming pattern.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 144 of 338 register name: bsrl register description: bert status register latched register address: 8eh bit # 7 6 5 4 3 2 1 0 name - - - - pmsl bel becl oosl default - - - - - - - - bit 3: performance monitor update status latched (pmsl) this bit is set when the pms bit transitions from 0 to 1. bit 2: bit error detected latched (bel) this bit is set when a bit error is detected. bit 1: bit error count latched (becl) this bit is set when the bec bit transitions from 0 to 1. bit 0: out of synchronization latched (oosl) this bit is set when the oos bit changes state. register name: bsrie register description: bert status register interrupt enable register address: 90h bit # 7 6 5 4 3 2 1 0 name - - - - pmsie beie becie oosie default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status interrupt enable (pmsie) this bit enables an interrupt if the pmsl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: bit error interrupt enable (beie) this bit enables an interrupt if the bel bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: bit error count interrupt enable (becie) this bit enables an interrupt if the becl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: out of synchronization interrupt enable (oosie) this bit enables an interrupt if the oosl bit is set. 0 = interrupt disabled 1 = interrupt enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 145 of 338 register name: rbecb0r register description: receive bit error count byte 0 register register address: 94h bit # 7 6 5 4 3 2 1 0 name bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit error count (bec[0:7]) lower eight bits of 24 bits. register description below. register name: rbecb1r register description: receive bit error count byte 1 register register address: 95h bit # 7 6 5 4 3 2 1 0 name bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit error count (bec[8:15]) eight bits of a 24 bit value. register description below. register name: rbecr2 register description: receive bit error count byte 2 register register address: 96h bit # 7 6 5 4 3 2 1 0 name bec23 bec22 bec21 bec20 bec19 bec18 bec17 bec16 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit error count (bec[16:23]) upper 8-bits of the register. bit error count (bec[0:23]) these twenty-four bits indicate the number of bit errors detected in the incoming data stream. this count stops incrementing when it reaches a count of ff ffffh. the associ ated bit error counter will not incremented when an oos condition exists.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 146 of 338 register name: rbcb0 register description: receive bit count byte 0 register register address: 98h bit # 7 6 5 4 3 2 1 0 name bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[0:7]) eight bits of a 32 bit value. register description below. register name: rbcb1 register description: receive bit count byte 1 register #1 register address: 99h bit # 7 6 5 4 3 2 1 0 name bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[8:15]) eight bits of a 32 bit value. register description below. register name: rbcb2 register description: receive bit count byte 2 register register address: 9ah bit # 7 6 5 4 3 2 1 0 name bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[16:23]) eight bits of a 32 bit value. register description below. register name: rbcb3 register description: receive bit count byte 3 register register address: 9bh bit # 7 6 5 4 3 2 1 0 name bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[24:31]) upper 8-bits of the register. bit count (bc[0:31]) these thirty-two bits indicate the number of bits in the incoming data stream. this count stops incrementing when it reaches a count of ffff ffffh. the associated bi t counter will not incremented when an oos condition exists.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 147 of 338 11.5 serial interface registers the serial interface contains the serial hdlc transport ci rcuitry and the associated serial port. the serial interface register map consists of registers that are comm on functions, transmit functions, and receive functions. bits that are underlined are read-only; all other bits can be written. all reserved registers and bits with ?-? designation should be written to zero, unless specifically not ed in the register definition. when read, the information from reserved registers and bits des ignated with ?-? should be discarded. counter registers are updated by asserting (low to high transition) the associated performance monitoring update signal (xxpmu). during the counter register update process, the associated performance monitoring status signal (xxpms) is deasserted. the counter register update process consists of loading the counter register with the current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then asserting xxpms. no events are missed during this update procedure. a latched bit is set when the associated event occurs, and remains set until it is cleared by reading. once cleared, a latched bit will not be set again until the associated event o ccurs again. reserved configuration bits and registers should be written to zero. 11.5.1 serial interface transmit and common registers serial interface transmit registers are used to control the hdlc transmitter associated with each serial interface. the register map is shown in the following table. note that throughout this document the hdlc processor is also referred to as a ?packet processor?. 11.5.2 serial interface transmit register bit descriptions register name: li.tslcr register description: transmit serial interface configuration register register address: 0c0h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tdenplt default 0 0 0 0 0 0 0 0 bit 0: transmit data enable polarity (tdenplt) if set to 1, tden is active low for enable. in the default mode, when tden is logic high, the data is enabled and output by the DS33R11. register name: li.rstpd register description: serial interface reset register register address: 0c1h bit # 7 6 5 4 3 2 1 0 name - - - - - - reset - default 0 0 0 0 0 0 0 0 bit 1: reset if this bit set to 1, the data path and control and status for this interface are reset. the serial interface is held in reset as long as this bit is high. this bit must be high for a minimum of 200ns for a valid reset to occur.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 148 of 338 register name: li.lpbk register description: serial interface loopback control register register address: 0c2h bit # 7 6 5 4 3 2 1 0 name - - - - - - - qlp default 0 0 0 0 0 0 0 0 bit 0: queue loopback enable (qlp) if this bit set to 1, data received on the serial interface is looped back to the serial interface transmitter. received data will not be sent from the serial interface to the ethernet interface. buffered packet data will remain in queue until the loopback is removed. 11.5.3 transmit hdlc processor registers register name: li.tppcl register description: transmit packet processor control low register register address: 0c4h bit # 7 6 5 4 3 2 1 0 name - - tfad tf16 tifv tsd tbre tiaei default 0 0 0 0 0 0 0 0 note: the user should take care not to modify this register value during packet error insertion. bits 5 - 6: transmit fcs append disable (tfad) ? this bit controls whether or not an fcs is appended to the end of each packet. when equal to 0, the calculated fcs bytes are appended to packets. when set to 1, packets are transmitted without fcs. in x.86 mode, fcs is always 32 bits and is always appended to the packet. bit 4: transmit fcs-16 enable (tf16) ? when 0, the fcs processing uses a 32-bit fcs. when 1, the fcs processing uses a 16-bit fcs. in x.86 mode, 32-bit fcs processing is always enabled, regardless of this bit. bit 3: transmit bit synchronous inter-frame fill value (tifv) ? when 0, inter-frame fill is done with the flag sequence (7eh). when 1, inter-frame fill is done with all '1's (ffh). this bit is ignored in x.86 mode and the interframe flag is always 7e. bit 2: transmit scrambling disable (tsd) ? when equal to 0, x 43 +1 scrambling is performed. when set to 1, scrambling is disabled. bit 1: transmit bit re ordering enable (tbre) ? when equal to 0, bit reordering is disabled (the first bit transmitted is from the msb of the transmit fifo byte tfd [7]). when set to 1, bit reordering is enabled (the first bit transmitted is from the lsb of the transmit fifo byte tfd [0]). bit 0: transmit initiate automatic error insertion (tiaei) ? this write-only bit initiates error insertion. see the li.tephc register definition for details of usage.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 149 of 338 register name: li.tifgc register description: transmit inter-frame gapping control register register address: 0c5h bit # 7 6 5 4 3 2 1 0 name tifg7 tifg6 tifg5 tifg4 tifg3 tifg2 tifg1 tifg0 default 0 0 0 0 0 0 0 1 bits 0 - 7: transmit inter-frame gapping (tifg[7:0]) ? these eight bits indicate the number of additional flags and bytes of inter-frame fill to be inserted between packets. the number of flags and bytes of inter-frame fill between packets is at least the value of tifg[7:0] plus 1. note: if inter-frame fill is set to all 1?s, a tfig value of 2 or 3 will result in a flag, two bytes of 1?s, and an additional flag between packets. register name: li.teplc register description: transmit errored packet low control register register address: 0c6h bit # 7 6 5 4 3 2 1 0 name tpen7 tpen6 tpen5 tpen 4 tpen3 tpen2 tpen1 tpen0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit errored packet insertion number (tpen[7:0]) ? these eight bits indicate the total number of errored packets to be transmitted when triggered by tiaei. error insertion will end after this number of errored packets have been transmitted. a value of ffh results in continuous errored packet insertion at the specified rate.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 150 of 338 register name: li.tephc register description: transmit errored packet high control register register address: 0c7h bit # 7 6 5 4 3 2 1 0 name meims tper6 tper5 tper 4 tper3 tper2 tper1 tper0 default 0 0 0 0 0 0 0 0 bit 7: manual error insert mode select (meims) ? when 0, the transmit manual error insertion signal (tmei) will not cause errors to be inserted. when 1, tmei will cause an error to be inserted when it transitions from a 0 to a 1. note: enabling tmei does not disable error insertion using tcer[6:0] and tcen[7:0]. bits 0 ? 6: transmit errored packet insertion rate (tper[6:0]) ? these seven bits indicate the rate at which errored packets are to be output. one out of every x * 10 y packets is to be an errored packet. tper[3:0] is the value x, and tper[6:4] is the value y which has a maximum value of 6. if tper[3:0] has a value of 0h errored packet insertion is disabled. if tper[6:4] has a value of 6xh or 7xh the errored packet rate is x * 10 6 . a tper[6:0] value of 01h results in every packet being errored. a tper[6:0] value of 0fh results in every 15 th packet being errored. a tper[6:0] value of 11h results in every 10 th packet being errored. to initiate automati c error insertion, use the following routine: 1) configure li.teplc and li.tephc for the desired error insertion mode. 2) write the li.tppcl.tiaei bit to 1. note that this bit is write-only. 3) if not using continuous error insertion (li.tpelc is not equal to ffh), the user should monitor the li.tppsr.tepf bit for completion of the error insertion. if interrupt on completion of error insertion is enabled (li.tppsrie.tepfie = 1), the user only needs to wait for the interrupt condition. 4) proceed with the cleanup routine listed below. cleanup routine: 1) write li.teplc and li.tephc each to 00h. 2) write the li.tppcl.tiaei bit to 0.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 151 of 338 register name: li.tppsr register description: transmit packet processor status register register address: 0c8h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tepf default 0 0 0 0 0 0 0 0 bit 0: transmit errored packet insertion finished (tepf) ? this bit is set when the number of errored packets indicated by the tpen[7:0] bits in the tepc register have been transmitted. this bit is cleared when errored packet insertion is disabled, or a new errored packet insertion process is initiated. register name: li.tppsrl register description: transmit packet processor status register latched register address: 0c9h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tepfl default - - - - - - - - bit 0: transmit errored packet insertion finished latched (tepfl) ? this bit is set when the tepf bit in the tppsr register transitions from zero to one. register name: li.tppsrie register description: transmit packet processor status register interrupt enable register address: 0cah bit # 7 6 5 4 3 2 1 0 name - - - - - - - tepfie default 0 0 0 0 0 0 0 0 bit 0: transmit errored packet insertion finished interrupt enable (tepfie) ? this bit enables an interrupt if the tepfl bit in the li.tppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 152 of 338 register name: li.tpcr0 register description: transmit packet count byte 0 register address: 0cch bit # 7 6 5 4 3 2 1 0 name tpc7 tpc6 tpc5 tpc4 tpc3 tpc2 tpc1 tpc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit packet count (tpc[7:0]) ? eight bits of 24 bit value. register description below. register name: li.tpcr1 register description: transmit packet count byte 1 register address: 0cdh bit # 7 6 5 4 3 2 1 0 name tpc15 tpc14 tpc13 tpc12 tpc11 tpc10 tpc9 tpc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit p acket count (tpc[15:8]) ? eight bits of 24 bit value. register description below. register name: li.tpcr2 register description: transmit packet count byte 2 register address: 0ceh bit # 7 6 5 4 3 2 1 0 name tpc23 tpc22 tpc21 tpc20 tpc19 tpc18 tpc17 tpc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit packet count (tpc[23:16]) ? these twenty-four bits indicate the number of packets extracted from the transmit fifo and output in the outgoing data stream.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 153 of 338 register name: li.tbcr0 register description: transmit byte count byte 0 register address: 0d0h bit # 7 6 5 4 3 2 1 0 name tbc7 tbc6 tbc5 tbc4 tbc3 tbc2 tbc1 tbc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[0:7]) ? eight bits of 32 bit value. register description below. register name: li.tbcr1 register description: transmit byte count byte 1 register address: 0d1h bit # 7 6 5 4 3 2 1 0 name tbc15 tbc14 tbc13 tbc12 tbc11 tbc10 tbc9 tbc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[15:8]) - eight bits of 32 bit value. register description below. register name: li.tbcr2 register description: transmit byte count byte 2 register address: 0d2h bit # 7 6 5 4 3 2 1 0 name tbc23 tbc22 tbc21 tbc20 tbc19 tbc18 tbc17 tbc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[23:16]) - eight bits of 32 bit value. register description below. register name: li.tbcr3 register description: transmit byte count byte 3 register address: 0d3h bit # 7 6 5 4 3 2 1 0 name tbc31 tbc30 tbc29 tbc28 tbc27 tbc26 tbc25 tbc24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[31:24]) ? these thirty-two bits indicate the number of packet bytes inserted in the outgoing data stream.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 154 of 338 register name: li.tmei register description: transmit manual error insertion register address: 0d4h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tmei default 0 0 0 0 0 0 0 0 bit 0: transmit manual error insertion (tmei) a zero to one transition will insert a single error in the transmit direction. register name: li.thpmuu register description: serial interface transmit hdlc pmu update register register address: 0d6h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tpmuu default 0 0 0 0 0 0 0 0 bit 0: transmit pmu update (tpmuu) this signal causes the transmit cell/packet processor block performance monitoring registers (counters) to be updated. a 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). this update updates performance monitoring counters for the serial interface. register name: li.thpmus register description: serial interface transmit hdlc pmu update status register register address: 0d7h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tpmus default 0 0 0 0 0 0 0 0 bit 0: transmit pmu update status (tpmus) this bit is set when the transmit pmu update is completed. this bit is cleared when tpmuu is reset.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 155 of 338 11.5.4 x.86 registers x.86 transmit and common registers are used to control the operation of the x.86 encoder and decoder. register name: li.tx86ede register description: x.86 encoding decoding enable register address: 0d8h bit # 7 6 5 4 3 2 1 0 name - - - - - - - x86ed default 0 0 0 0 0 0 0 0 bit 0: x.86 encoding decoding (x86ed) if this bit is set to 1, x.86 encoding and decoding is enabled for the transmit and receive paths. the mac frame is encapsulated in the x.86 frame for transmit and the x.86 headers are checked for in the received data. if x.86 functionality is selected, the x.86 receiver byte boundary is provided by the rbsync signal and the DS33R11 provides the transmit byte synchronization tbsync. no hdlc encapsulation is performed. register name: li.trx86a register description: transmit receive x.86 address register address: 0d9h bit # 7 6 5 4 3 2 1 0 name x86tra7 x86tra6 x86tra5 x86tra 4 x86tra3 x86tra2 x86tra1 x86tra0 default 0 0 0 0 0 1 0 0 bits 0 - 7: x86 transmit receive address (x86tra0-7) this is the address field for the x.86 transmitter and for the receiver. the register default value is 0x04. register name: li.trx8c register description: transmit receive x.86 control register address: 0dah bit # 7 6 5 4 3 2 1 0 name x86trc7 x86trc6 x86trc5 x86trc4 x86trc3 x86trc2 x86trc1 x86trc0 default 0 0 0 0 0 0 1 1 bits 0 - 7: x86 transmit receive control (x86trc0-7) this is the control field for the x.86 transmitter and expected value for the receiver. the register is reset to 0x03 register name: li.trx86sapih register description: transmit receive x.86 sapih register address: 0dbh bit # 7 6 5 4 3 2 1 0 name trsapih7 trsapih6 trsapih5 trsapih4 trsapih3 trsapih2 trsapih1 trsapih0 default 1 1 1 1 1 1 1 0 bits 0 - 7: x86 transmit receive address (trsapih0-7) this is the address field for the x.86 transmitter and expected for the receiver. the register is reset to 0xfe.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 156 of 338 register name: li.trx86sapil register description: transmit receive x.86 sapil register address: 0dch bit # 7 6 5 4 3 2 1 0 name trsapil7 trsapil6 trsapil5 trsapil4 trsapil3 trsapil2 trsapil1 trsapil0 default 0 0 0 0 0 0 0 1 bits 0 ? 7: x86 transmit receive control (trsapil0-7) this is the address field for the x.86 transmitter and expected value for the receiver. the register is reset to 0x01 register name: li.cir register description: committed information rate register address: 0ddh bit # 7 6 5 4 3 2 1 0 name cire cir6 cir5 cir4 cir3 cir2 cir1 cir0 default 0 0 0 0 0 0 0 1 bit 7: committed information rate enable (cire) set this bit to 1 to enable the committed information rate controller feature. bits 0 ? 6: committed information rate (cir0-6) these bits provide the value for the committed information rate. the value is multiplied by 500kbit/s to get the cir value. the user must ensure that the cir value is less than or equal to the maximum serial interface transmit rate. the valid range is from 1 to 104. any values outside this range will result in unpredictable behavior. note that a value of 104 translates to a 52mbit/s line rate. hence if the cir is above the line rate, the rate is not restricted by the cir. for instance - if using a t1 line and the cir is programmed with a value of 104, it has no effect in restricting the rate.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 157 of 338 11.5.5 receive serial interface serial receive registers are used to control the hdlc receiver associated with each serial interface. note that throughout this document hdlc processor is also referred to as ?packet processor?. the receive packet processor block has seventeen registers. 11.5.5.1 register bit descriptions register name: li.rslcr register description: receive serial interface configuration register register address: 100h bit # 7 6 5 4 3 2 1 0 name - - - - - - - rdenplt default 0 0 0 0 0 0 0 0 bit 0: receive data enable polarity (rdenplt) receive data enable polarity. if set to 1, rden low enables reception of the bit. register name: li.rppcl register description: receive packet processor control low register register address: 101h bit # 7 6 5 4 3 2 1 0 name - - rfpd rf16 rfed rdd rbre rcce default 0 0 0 0 0 0 0 0 bit 5: receive fcs processing disable (rfpd) ? when equal to 0, fcs processing is performed and fcs is appended to packets. when set to 1, fcs processing is disabled (the packets do not have an fcs appended). in x.86 mode, fcs processing is always enabled. bit 4: receive fcs-16 enable (rf16) ? when 0, the error checking circuit uses a 32-bit fcs. when 1, the error checking circuit uses a 16-bit fcs. this bit is ignored when fcs processing is disabled. in x.86 mode, the fcs is always 32 bits. bit 3: receive fcs extraction disable (rfed) ? when 0, the fcs bytes are discarded. when 1, the fcs bytes are passed on. this bit is ignored when fcs processing is disabled. in x.86 mode, fcs bytes are discarded. bit 2: receive descrambling disable (rdd) ? when equal to 0, x 43 +1 descrambling is performed. when set to 1, descrambling is disabled. bit 1: receive bit re ordering enable (rbre) ? when equal to 0, reordering is disabled and the first bit received is expected to be the msb dt [7] of the byte. when set to 1, bit reordering is enabled and the first bit received is expected to be the lsb dt [0] of the byte. bit 0: receive clear channel enable (rcce) ? when equal to 0, packet processing is enabled. when set to 1, the device is in clear channel mode and all packet-processing functions except descrambling and bit reordering are disabled.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 158 of 338 register name: li.rmpscl register description: receive maximum packet size control low register register address: 102h bit # 7 6 5 4 3 2 1 0 name rmx7 rmx6 rmx5 rmx4 rmx3 rmx2 rmx1 rmx0 default 1 1 1 0 0 0 0 0 bits 0 - 7: receive maximum packet size (rmx[7:0]) eight bits of a sixteen bit val ue. register description below. register name: li.rmpsch register description: receive maximum packet size control high register register address: 103h bit # 7 6 5 4 3 2 1 0 name rmx15 rmx14 rmx13 rmx12 rmx11 rmx10 rmx9 rmx8 default 0 0 0 0 0 1 1 1 bits 0-7: receive maximum packet size (rmx[8:15]) these sixteen bits indicate the maximum allowable packet size in bytes. the size includes the fcs bytes, but excludes bit/byte stuffing. note: if the maximum packet size is less than the minimum packet size, all packets are discarded. when packet processing is disabled, these sixteen bits indicate the "packet" size the incoming data is to be broken into. the maximum packet size allowable is 2016 bytes plus the fcs bytes. any values programmed that are greater than 2016 + fcs will have the same effect as 2016+ fcs value. in x.86 mode, the x.86 encapsulation bytes are included in maximum size control. register name: li.rppsr register description: receive packet processor status register register address: 104h bit # 7 6 5 4 3 2 1 0 name - - - - - repc rapc rspc default 0 0 0 0 0 0 0 0 bit 2: receive fcs errored packet count (repc) this read only bit indicates that the receive fcs errored packet count is nonzero. bit 1: receive aborted packet count (rapc) this read only bit indicates that the receive aborted packet count is nonzero. bit 0: receive size violation packet count (rspc) this read only bit indicates t hat the receive size violation packet count is nonzero.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 159 of 338 register name: li.rppsrl register description: receive packet processor status register latched register address: 105h bit # 7 6 5 4 3 2 1 0 name repl rapl ripdl rspdl rlpdl repcl rapcl rspcl default - - - - - - - - bit 7: receive fcs errored packet latched (repl) this bit is set when a packet with an errored fcs is detected. bit 6: receive aborted packet latched (rapl) this bit is set when a packet with an abort indication is detected. bit 5: receive invalid packet detected latched (ripdl) this bit is set when a packet with a noninteger number of bytes is detected. bit 4: receive small packet detected latched (rspdl) this bit is set when a packet smaller than the minimum packet size is detected. bit 3: receive large packet detected latched (rlpdl) this bit is set when a packet larger than the maximum packet size is detected. bit 2: receive fcs errored packet count latched (repcl) this bit is set when the repc bit in the rppsr register transitions from zero to one. bit 1: receive aborted p acket count latched (rapcl) this bit is set when the rapc bit in the rppsr register transitions from zero to one. bit 0: receive size violati on packet count latched (rspcl) this bit is set when the rspc bit in the rppsr register transitions from zero to one.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 160 of 338 register name: li.rppsrie register description: receive packet processor status register interrupt enable register address: 106h bit # 7 6 5 4 3 2 1 0 name repie rapie ripdie rspdie rlpdie repcie rapcie rspcie default 0 0 0 0 0 0 0 0 bit 7: receive fcs errored packet interrupt enable (repie) this bit enables an interrupt if the repl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 6: receive aborted packet interrupt enable (rapie) this bit enables an interrupt if the rapl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 5: receive invalid packet detected interrupt enable (ripdie) this bit enables an interrupt if the ripdl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 4: receive small packet detected interrupt enable (rspdie) this bit enables an interrupt if the rspdl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 3: receive large packet detected interrupt enable (rlpdie) this bit enables an interrupt if the rlpdl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: receive fcs errored packet count interrupt enable (repcie) this bit enables an interrupt if the repcl bit in the li.rppsrl register is set. must be set low when the packets do not have an fcs appended. 0 = interrupt disabled 1 = interrupt enabled bit 1: receive aborted packet c ount interrupt enable (rapcie) this bit enables an interrupt if the rapcl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: receive size violation packet count interrupt enable (rspcie) this bit enables an interrupt if the rspcl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 161 of 338 register name: li.rpcb0 register description: receive packet count byte 0 register register address: 108h bit # 7 6 5 4 3 2 1 0 name rpc7 rpc6 rpc5 rpc4 rpc3 rpc2 rpc1 rpc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive packet count (rpc [7:0]) eight bits of a 24-bit value. register description below. register name: li.rpcb1 register description: receive packet count byte 1 register register address: 109h bit # 7 6 5 4 3 2 1 0 name rpc15 rpc14 rpc13 rpc12 rpc11 rpc10 rpc09 rpc08 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive packet count (rpc [15:8]) eight bits of a 24-bit value. register description below. register name: li.rpcb2 register description: receive packet count byte 2 register register address: 10ah bit # 7 6 5 4 3 2 1 0 name rpc23 rpc22 rpc21 rpc20 rpc19 rpc18 rpc17 rpc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive p acket count (rpc [23:16]) these twenty-four bits indicate the number of packets stored in the receive fifo without an abort indication. note: pa ckets discarded due to system loopback or an overflow condition are included in this count. this register is valid when clear channel is enabled.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 162 of 338 register name: li.rfpcb0 register description: receive fcs errored packet count byte 0 register register address: 10ch bit # 7 6 5 4 3 2 1 0 name rfpc7 rfpc6 rfpc5 rfpc4 rfpc3 rfpc2 rfpc1 rfpc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive fcs erro red packet count (rfpc[7:0]) eight bits of a 24-bit value. register description below. register name: li.rfpcb1 register description: receive fcs errored packet count byte 1 register register address: 10dh bit # 7 6 5 4 3 2 1 0 name rfpc15 rfpc14 rfpc13 rfpc12 rfpc11 rfpc10 rfpc9 rfpc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive fcs erro red packet count (rfpc[15:8]) eight bits of a 24-bit value. register description below. register name: li.rfpcb2 register description: receive fcs errored packet count byte 2 register register address: 10eh bit # 7 6 5 4 3 2 1 0 name rfpc23 rfpc22 rfpc21 rfpc20 rfpc19 rfpc18 rfpc17 rfpc16 default 0 0 0 0 0 0 0 0 receive fcs errored p acket count (rfpc[23:16]) these twenty-four bits indicate the number of packets received with an fcs error. the byte count for these packets is included in the receive aborted byte count register rebcr.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 163 of 338 register name: li.rapcb0 register description: receive aborted packet count byte 0 register register address: 110h bit # 7 6 5 4 3 2 1 0 name rapc7 rapc6 rapc5 rapc4 rapc3 rapc2 rapc1 rapc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborte d packet count (rapc [7:0]) eight bits of a 24-bit value. register description below. register name: li.rapcb1 register description: receive aborted packet count byte 1 register register address: 111h bit # 7 6 5 4 3 2 1 0 name rapc15 rapc14 rapc13 rapc12 rapc11 rapc10 rapc9 rapc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborted packet count (rapc[15:8]) eight bits of a 24-bit value. register description below. register name: li.rapcb2 register description: receive aborted packet count byte 2 register register address: 112h bit # 7 6 5 4 3 2 1 0 name rapc23 rapc22 rapc21 rapc20 rapc19 rapc18 rapc17 rapc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive aborte d packet count (rapc [23:16]) the twenty-four bit value from these three registers indicates the number of packets received with a packet abort indication. the byte count for these packets is included in the receive aborted byte count register rebcr.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 164 of 338 register name: li.rspcb0 register description: receive size violation packet count byte 0 register register address: 114h bit # 7 6 5 4 3 2 1 0 name rspc7 rspc6 rspc5 rspc4 rspc3 rspc2 rspc1 rspc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive size violation packet count (rspc [7:0]) eight bits of a 24-bit value. register description below. register name: li.rspcb1 register description: receive size violation packet count byte 1 register register address: 115h bit # 7 6 5 4 3 2 1 0 name rspc15 rspc14 rspc13 rspc12 rspc11 rspc10 rspc9 rspc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive size violation packet count (rspc [15:8]) eight bits of a 24-bit value. register description below. register name: li.rspcb2 register description: receive size violation packet count byte 2 registers register address: 116h bit # 7 6 5 4 3 2 1 0 name rspc23 rspc22 rspc21 rspc20 rspc19 rspc18 rspc17 rspc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive size viol ation packet count (rspc [23:16]) these twenty-four bits indicate the number of packets received with a packet size violation (below minimum, above maximum, or noninteger number of bytes). the byte count for these packets is included in the receive aborted byte count register rebcr.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 165 of 338 register name: li.rbc0 register description: receive byte count 0 register register address: 118h bit # 7 6 5 4 3 2 1 0 name rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive byte count (rbc [7:0]) eight bits of a 32-bit value. register description below. register name: li.rbc1 register description: receive byte count 1 register register address: 119h bit # 7 6 5 4 3 2 1 0 name rbc15 rbc14 rbc13 rbc12 rbc11 rbc10 rbc9 rbc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive byte count (rbc [15:8]) eight bits of a 32-bit value. register description below. register name: li.rbc2 register description: receive byte count 2 register register address: 11ah bit # 7 6 5 4 3 2 1 0 name rbc23 rbc22 rbc21 rbc20 rbc19 rbc18 rbc17 rbc16 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive byte count (rbc [23:16]) eight bits of a 32-bit value. register description below. register name: li.rbc3 register description: receive byte count 3 register register address: 11bh bit # 7 6 5 4 3 2 1 0 name rbc31 rbc30 rbc29 rbc28 rbc27 rbc26 rbc25 rbc24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive by te count (rbc [31:24]) these thirty-two bits indicate the number of bytes contained in packets stored in the receive fifo without an abort indica tion. note: bytes discarded due to fcs extraction, system loopback, fifo reset, or an overflow condition may be included in this count.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 166 of 338 register name: li.rac0 register description: receive aborted byte count 0 register register address: 11ch bit # 7 6 5 4 3 2 1 0 name rebc7 rebc6 rebc5 rebc4 rebc3 rebc2 rebc1 rebc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive abor ted byte count (rbc [7:0]) eight bits of a 32-bit value. register description below. register name: li.rac1 register description: receive aborted byte count 1 register register address: 11dh bit # 7 6 5 4 3 2 1 0 name rebc15 rebc14 rebc13 rebc12 rebc11 rebc10 rebc9 rebc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborte d byte count (rbc [15:8]) eight bits of a 32-bit value. register description below. register name: li.rac2 register description: receive aborted byte count 2 register register address: 11eh bit # 7 6 5 4 3 2 1 0 name rebc23 rebc22 rebc21 rebc20 rebc19 rebc18 rebc17 rebc16 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborte d byte count (rbc [16:23]) eight bits of a 32-bit value. register description below. register name: li.rac3 register description: receive aborted byte count 3 register register address: 11fh bit # 7 6 5 4 3 2 1 0 name rebc31 rebc30 rebc29 rebc28 rebc27 rebc26 rebc25 rebc24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive aborted byte count (rebc[31:24]) these thirty-two bits indicate the number of bytes contained in packets stored in the receive fifo with an abort indication. note: bytes discarded due to fcs extraction, system loopback, fifo reset, or an overflow condition may be included in this count.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 167 of 338 register name: li.rhpmuu register description: serial interface receive hdlc pmu update register register address: 120h bit # 7 6 5 4 3 2 1 0 name - - - - - - - rpmuu default 0 0 0 0 0 0 0 0 bit 0: receive pmu update (rpmuu) this signal causes the receive cell/packet processor block performance monitoring registers (counters) to be updated. a 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). this update updates performance monitoring counters for the serial interface. register name: li.rhpmus register description: serial interface receive hdlc pmu update status register register address: 121h bit # 7 6 5 4 3 2 1 0 name - - - - - - - rpmuus default 0 0 0 0 0 0 0 0 bit 0: receive pmu update status (rpmuus) this bit is set when the transmit pmu update is completed. this bit is cleared when rpmuu is set to 0. register name: li.rx86s register description: receive x.86 latched status register register address: 122h bit # 7 6 5 4 3 2 1 0 name - - - - sapihne sapilne cne ane default - - - - - - - - bit 3: sapi high is not equal to li.trx86sapih latched status (sapihne) this latched status bit is set if sapih is not equal to li.trx86sapih. this latched status bit is cleared upon read. bit 2: sapi low is not equal to li.trx86sapil latched status (sapilne) this latched status bit is set if sapil is not equal to li.trx86sapil. this latched status bit is cleared upon read. bit 1: control is not equal to li.trx8c (cne) this latched status bit is set if the control field is not equal to li.trx8c . this latched status bit is cleared upon read. bit 0: address is not equal to li.trx86a (ane) this latched status bit is set if the x.86 address field is not equal to li.trx86a . this latched status bit is cleared upon read.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 168 of 338 register name: li.rx86lsie register description: receive x.86 interrupt enable register address: 123h bit # 7 6 5 4 3 2 1 0 name - - - - sapine01im sapinefeim cne3lim ane4im default 0 0 0 0 0 0 0 0 bit 3: sapi octet not equal to li.trx86sapih interrupt enable (sapine01im) if this bit is set to 1, li.rx86s.sapihne will generate an interrupt. bit 2: sapi octet not equal to li.trx86sapil interrupt enable (sapinefeim) if this bit is set to 1, li.rx86s.sapilne will generate an interrupt. bit 1: control not equal to li.trx8c interrupt enab le (cne3lim) if this bit is set to 1, li.rx86s.cne will generate an interrupt. bit 0: address not equal to li.trx86a interrupt enable (ane4im) if this bit is set to 1, li.rx86s.ane will generate an interrupt. register name: li.tqlt register description: serial interface transmit queue low threshold (watermark) register address: 124h bit # 7 6 5 4 3 2 1 0 name tqlt7 tqlt6 tqlt5 tqlt4 tqlt3 tqlt2 tqlt1 tqlt0 default 0 0 0 0 0 0 0 0 bits 0 - 7: transmit queue low threshold (tqlt[0:7]) the transmit queue low threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold. note that the transmit queue is for data that was received from the serial interface to be sent to the ethernet interface. register name: li.tqht register description: serial interface transmit queue high threshold (watermark) register address: 125h bit # 7 6 5 4 3 2 1 0 name tqht7 tqht6 tqht5 tqht4 tqht3 tqht2 tqht1 tqht0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit queue high threshold (tqht[0:7]) the transmit queue high threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold. note that the transmit queue is for data that was received from the serial interface to be sent to the ethernet interface.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 169 of 338 register name: li.tqtie register description: serial interface transmit queue cross threshold interrupt enable register address: 126h bit # 7 6 5 4 3 2 1 0 name - - - - tfovfie tqovfie tqhtie tqltie default 0 0 0 0 0 0 0 0 bit 3: transmit fifo overflow for connection interrupt enable (tfovfie) if this bit is set, the watermark interrupt is enabled for tfovfls. bit 2: transmit queue overflow for connection interrupt enable (tqovfie) if this bit is set, the watermark interrupt is enabled for tqovfls. bit 1: transmit queue for connection high threshold interrupt enable (tqhtie) if this bit is set, the watermark interrupt is enabled for tqhts. bit 0: transmit queue for connection low threshold interrupt enable (tqltie) if this bit is set, the watermark interrupt is enabled for tqlts. register name: li.tqctls register description: serial interface transmit queue cross threshold latched status register address: 127h bit # 7 6 5 4 3 2 1 0 name - - - - tfovfls tqovfls tqhtls tqltls default - - - - - - - - bit 3: transmit queue fifo overflowed latched status (tfovfls) this bit is set if the transmit queue fifo has overflowed. this register is cleared after a read. this fifo is for data to be transmitted from the hdlc to be sent to the sdram. bit 2: transmit queue overflow latched status (tqovfls) this bit is set if the transmit queue has overflowed. this register is cleared after a read. bit 1: transmit queue for connection exceeded high threshold latched status (tqhtls) this bit is set if the transmit queue crosses the high watermark. this register is cleared after a read. bit 0: transmit queue for connection exceeded low threshold latched status (tqltls) this bit is set if the transmit queue crosses the low watermark. this register is cleared after a read.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 170 of 338 11.6 ethernet interface registers the ethernet interface registers are used to configure rmii/mii bus operation and establish the mac parameters as required by the user. the mac registers cannot be addressed directly from the processor port. the registers below are used to perform indirect read or write operations to t he mac registers. the mac status registers are shown in table 11-7 . accessing the mac registers is described in the section 9.15 . 11.6.1 ethernet interface register bit descriptions register name: su.macradl register description: mac read address low register register address: 140h bit # 7 6 5 4 3 2 1 0 name macra7 macra6 macra5 ma cra4 macra3 macra 2 macra1 macra0 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra0-7) low byte of the mac indirect register address. used only for read operations. register name: su.macradh register description: mac read address high register register address: 141h bit # 7 6 5 4 3 2 1 0 name macra15 macra14 macra13 macra 12 macra11 macra10 macra9 macra8 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra8-15) high byte of the mac indirect register address. used only for read operations. register name: su.macrd0 register description: mac read data byte 0 register address: 142h bit # 7 6 5 4 3 2 1 0 name macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 0 (macrd0-7) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc .mcs bit is zero.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 171 of 338 register name: su.macrd1 register description: mac read data byte 1 register address: 143h bit # 7 6 5 4 3 2 1 0 name macrd15 macrd14 macrd13 macrd1 2 macrd11 macrd10 macrd9 macrd8 0 0 0 0 0 0 0 0 bits 0 - 7: mac read data 1 (macrd8-15) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc .mcs bit is zero. register name: su.macrd2 register description: mac read data byte 2 register address: 144h bit # 7 6 5 4 3 2 1 0 name macrd23 macrd22 macrd21 macrd2 0 macrd19 macrd18 macrd17 macrd16 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 2 (macrd16-23) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc.mcs bit is zero. register name: su.macrd3 register description: mac read data byte 3 register address: 145h bit # 7 6 5 4 3 2 1 0 name macrd31 macrd30 macrd29 macrd2 8 macrd27 macrd26 macrd25 macrd24 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 3 (macrd24-31) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc.mcs bit is zero. register name: su.macwd0 register description: mac write data 0 register address: 146h bit # 7 6 5 4 3 2 1 0 name macwd7 macwd6 macwd5 macw d4 macwd3 macwd2 macwd1 macwd0 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 0 (macwd0-7) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc.mcs bit is zero.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 172 of 338 register name: su.macwd1 register description: mac write data 1 register address: 147h bit # 7 6 5 4 3 2 1 0 name macwd15 macwd14 macwd13 macwd 12 macwd11 macwd10 macwd09 macwd08 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 1 (macwd8-15) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc .mcs bit is zero. register name: su.macwd2 register description: mac write data register 2 register address: 148h bit # 7 6 5 4 3 2 1 0 name macwd23 macwd22 macwd21 macwd 20 macwd19 macwd18 macwd17 macwd16 0 0 0 0 0 0 0 0 bits 0 - 7: mac write data 2 (macwd16-23) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc.mcs bit is zero. register name: su.macwd3 register description: mac write data 3 register address: 149h bit # 7 6 5 4 3 2 1 0 name macd31 macd30 macd29 macd 28 macd27 macd26 macd25 macd24 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 3 (macd24-31) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc.mcs bit is zero. register name: su.macawl register description: mac address write low register address: 14ah bit # 7 6 5 4 3 2 1 0 name macaw 7 macaw 6 macaw 5 macaw 4 macaw3 macaw2 macaw1 macaw0 0 0 0 0 0 0 0 0 bits 0 -7: mac write address (macaw0-7) low byte of the mac indirect write address. used only for write operations.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 173 of 338 register name: su.macawh register description: mac address write high register address: 14bh bit # 7 6 5 4 3 2 1 0 name macaw 15 macaw 14 macaw 13 maca w12 macaw11 macaw10 macaw9 macaw8 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write address (macaw8-15) high byte of the mac indirect write address. used only for write operations. register name: su.macrwc register description: mac read write command status register address: 14ch bit # 7 6 5 4 3 2 1 0 name - - - - - - mcrw mcs default 0 0 0 0 0 0 0 0 bit 1: mac command rw (mcrw) if this bit is written to 1, a read is performed from the mac. if this bit is written to 0, a write operation is performed. address information for write operations must be located in su.macawh and su.macawl . address information for read operations must be located in su.macradh and su.macradl . the user must also write a 1 to the mcs bit, and the DS33R11 will clear mcs when the operation is complete. bit 0: mac command status (mcs) setting mcs in conjunction with mcrw will initiate a read or write to the mac registers. upon completion of the read or write this bit is cleared. once a read or write command has been initiated the host must poll this bit to see when the operation is complete.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 174 of 338 register name: su.lpbk register description: ethernet interface loopb ack control register register address: 14fh bit # 7 6 5 4 3 2 1 0 name - - - - - - - qlp default 0 0 0 0 0 0 0 0 bit 0: queue loopback enable (qlp) if this bit is set to 1, data from the ethernet interface receive queue is looped back to the transmit queue. buffered data from the serial interface will remain until the loopback is removed. register name: su.gcr register description: ethernet interface general control register register address: 150h bit # 7 6 5 4 3 2 1 0 name - - - - crcs h 10s atflow jame default 0 0 0 0 0 0 1 0 bit 3: crcs if this bit is zero (default), the received mac or ethernet frame crc is stripped before the data is encapsulated and transmitted on the serial interface. data received from the serial interface is decapsulated, a crc is recalculated and appended to the packet for transmission to the ethernet interface. if this bit is set to 1, the crc is not stripped from received packets prior to encapsul ation and transmission to the serial interface, and data received from the serial interface is decapsulated directly. no crc recalculation is performed on data received from the serial interface. note that the maximum packet size supported by the ethernet interface is still 2016 (this includes the 4 bytes of crc). bit 2: h10s if this bit is set the mac will operate at 100 mbit/s. if this bit is zero, the mac will operate at 10 mbit/s. this bit controls the 10/100 selection for rmii and dce mode. in dte and mii mode, the mac determines the data rate from the incoming tx_clk and rx_clk. bit 1: automatic flow control enable (atflow) if this bit is set to 1, automatic flow control is enabled based on the connection receive queue size and high watermarks. pause frames are sent automatically in full duplex mode. the pause time must be programmed through su.macfcr . the jam sequence will not be sent automatically in half duplex mode unless the jame bit is set. th is bit is applicable only in software mode. bit 0: jam enable (jame) if this bit is set to 1, a jam sequence is sent for a duration of 4 bytes. this function is only valid in half duplex mode, and will only function if automati c flow control is disabled. note that if the receive queue size is less than receive high threshold, setting a jame will jam one received frame. if jame is set and the receiver queue size is higher than the high threshold, all received frames are jammed until the queue empties below the threshold. note that su.gcr is only valid in the software mode.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 175 of 338 register name: su.tfrc register description: transmit frame resend control register address: 151h bit # 7 6 5 4 3 2 1 0 name - - - - ncfq tp dfcb tprhbc tprcb default 0 0 0 0 0 0 0 0 bit 3: no carrier queue flush bar (ncfq) if this bit is set to 1, the queue for data passing from serial interface to ethernet interface will not be flushed when loss of carrier is detected. bit 2: transmit packet deferred fail control enable (tpdfcb) if this bit if set to 1, the current frame is transmitted immediately instead of being deferred. if this bit is set to 0, the frame is deferred if crs is asserted and sent when the crs is unasserted indicating the media is idle. bit 1: transmit packet hb fail control bar (tprhbc) if this bit is set to 1, the current frame will not be retransmitted if a heartbeat failure is detected. bit 0: transmit packet resend control bar (tprcb) if this bit is set to 1, the current frame will not be retransmitted if any of the following errors have occurred:  jabber time out  loss of carrier  excessive deferral  late collision  excessive collisions  under run  collision note that blocking retransmission due to collision (applicabl e in miii/half duplex mode) can result in unpredictable system level behavior.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 176 of 338 register name: su.tfsl register description: transmit frame status low register address: 152h bit # 7 6 5 4 3 2 1 0 name ur ec lc ed loc noc - fabort default 0 0 0 0 0 0 0 0 bit 7: under run (ur) when this bit is set to 1, the frame was aborted due to a data under run condition of the transmit buffer. bit 6: excessive collisions (ec) when this bit is set to 1, a frame has been aborted after 16 successive collisions while attempting to transmit the current frame. if the disable retry bit is set to 1, then excessive collisions will be set to 1 after the first collision. bit 5: late collision (lc) when this bit is set to 1, a frame was aborted by collision after the 64 bit collision window. not valid if an under run has occurred. bit 4: excessive deferral (ed) when this bit is set to 1, a frame was aborted due to excessive deferral. bit 3: loss of carrier (loc) when this bit is set to 1, a frame was aborted due to loss of carrier for one or more bit times. valid only for noncollided fram es. valid only in half-duplex operation. bit 2: no carrier (noc) when this bit is set to 1, a frame was aborted because no carrier was found for transmission. bit 1: reserved bit 0: frame abort (fabort) when this bit is set to 1, the mac has aborted a frame for one of the above reasons. when this bit is clear, the previous frame has been transmitted successfully. register name: su.tfsh register description: transmit frame status high register address: 153h bit # 7 6 5 4 3 2 1 0 name pr hbf cc3 cc2 cc1 cc0 lco def default 0 0 0 0 0 0 0 0 bit 7: packet resend (pr) when this bit is set, the current packet must be retransmitted due to a collision. bit 6: heartbeat failure (hbf) when this bit is set, the device failed to detect a heart beat after transmission. this bit is not valid if an under run has occurred. bits 2-5: collision count (cc0-3) these 4 bits indicate the number of collisions that occurred prior to successful transmission of the previous frame. not valid if excessive collisions is set to 1. bit 1: late collision (lco) when set to 1, the mac observed a collision after the 64-byte collision window. bit 0: deferred frame (def) when set to 1, the current frame was deferred due to carrier assertion by another node after being ready to transmit.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 177 of 338 register name: su.rfsb0 register description: receive frame status byte 0 register address: 154h bit # 7 6 5 4 3 2 1 0 name fl7 fl6 fl5 fl4 fl3 fl2 fl1 fl0 default 0 0 0 0 0 0 0 0 bits 0 - 7: frame length (fl[0:7]) these 8 bits are the low byte of the length (in bytes) of the received frame, with fcs and padding. if automatic pad stripping is enabled, this value is the length of the received packet without pcs or pad bytes. the upper 6 bits are contained in su.rfsb1. register name: su.rfsb1 register description: receive frame status byte 1 register address: 155h bit # 7 6 5 4 3 2 1 0 name rf wt fl13 fl12 fl11 fl10 fl9 fl8 default 0 0 0 0 0 0 0 0 bit 7: runt frame (rf) this bit is set to 1 if the received frame was altered by a collision or terminated within the collision window. bit 6: watchdog timeout (wt) this bit is set to 1 if a packet receive time exceeds 2048 byte times. after 2048 byte times the receiver is disabled and the received frame will fail crc check. bits 0-5: frame length (fl[8:13]) these 6 bits are the upper bits of the length (in bytes) of the received frame, with fcs and padding. if automatic pad stripping is enabled, this value is the length of the received packet without pcs or pad bytes. register name: su.rfsb2 register description: receive frame status byte 2 register address: 156h bit # 7 6 5 4 3 2 1 0 name - - crce db m iie ft cs ftl default 0 0 0 0 0 0 0 0 bit 5: crc error (crce) this bit is set to 1 if the received frame does not contain a valid crc value. bit 4: dribbling bit (db) this bit is set to 1 if the received frame contains a noninteger multiple of 8 bits. it does not indicate that the frame is invalid. this bit is not valid for runt or collided frames. bit 3: mii error (miie) this bit is set to 1 if an error was found on the mii bus. bit 2: frame type (ft) this bit is set to 1 if the received frame exceeds 1536 bytes. it is equal to zero if the received frame is an 802.3 frame. this bit is not valid for runt frames. bit 1: collision seen (cs) this bit is set to 1 if a late collision occurred on the received packet. a late collision is one that occurs after the 64 byte collision window. bit 0: frame too long (ftl) this bit is set to 1 if a frame exceeds the 1518 byte maximum standard ethernet frame. this bit is only an indication, and causes no frame truncation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 178 of 338 register name: su.rfsb3 register description: receive frame status byte 3 register address: 157h bit # 7 6 5 4 3 2 1 0 name mf - - bf mcf uf cf le default 0 0 0 0 0 0 0 0 bit 7: missed frame (mf) this bit is set to 1 if the packet is not successfully received from the mac by the packet arbiter. bit 4: broadcast frame (bf) this bit is set to 1 if the current frame is a broadcast frame. bit 3: multicast frame (mcf) this bit is set to 1 if the current frame is a multicast frame. bit 2: unsupported control frame (uf) this bit is set to 1 if the frame received is a control frame with an opcode that is not supported. if the control frame bit is set, and the unsupported control frame bit is clear, then a pause frame has been received and the transmitter is paused. bit 1: control frame (cf) this bit is set to 1 when the current frame is a control frame. this bit is only valid in full- duplex mode. bit 0: length error (le) this bit is set to 1 when the frames length field and the actual byte count are unequal. this bit is only valid for 802.3 frames.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 179 of 338 register name: su.rmfsrl register description: receiver maximum frame low register register address: 158h bit # 7 6 5 4 3 2 1 0 name rmps7 rmps6 rmps5 rmps4 rmps3 rmps2 rmps1 rmps0 default 1 1 1 0 0 0 1 0 bits 7- 0: receiver maximum frame (rmps[0:7]) eight bits of sixteen bit val ue. register description below. register name: su.rmfsrh register description: receiver maximum frame high register register address: 159h bit # 7 6 5 4 3 2 1 0 name rmps15 rmps14 rmps13 rmps12 rmps11 rmps10 rmps9 rmps8 default 0 0 0 0 0 1 1 1 bits 7- 0: receiver maximum frame (rmps[8:15]) this value is the receiver?s maximum frame size (in bytes), up to a maximum of 2016 bytes. any frame received greater than this value is rejected. the frame size includes destination address, source address, type/length, data and crc-32. the frame size is not the same as the frame length encoded within the ieee 802.3 frame. any values programmed that are greater than 2016 will have unpredictable behavior and should be avoided. register name: su.rqlt register description: receive queue low threshold (watermark) register address: 15ah bit # 7 6 5 4 3 2 1 0 name rqlt7 rqlt6 rqlt5 rqlt4 rqlt3 rqlt2 rqlt1 rqlt0 default 0 0 1 1 0 1 1 1 bits 0 - 7: receive queue low threshold (rqlt[0:7]) the receive queue low threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold. note that the receive queue is for data that was received from the ethernet interface to be sent to the serial interface. register name: su.rqht register description: receive queue high threshold (watermark) register address: 15bh bit # 7 6 5 4 3 2 1 0 name rqht7 rqht6 rqht5 rqht 4 rqht3 rqht2 rqht1 rqht0 default 0 0 1 1 1 0 1 0 bits 0 ? 7: receive queue high threshold (rqth[0:7]) the receive queue high threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold. note that the receive queue is for data that was received from the ethernet interface to be sent to the serial interface.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 180 of 338 register name: su.qrie register description: receive queue cross threshold enable register address: 15ch bit # 7 6 5 4 3 2 1 0 name - - - - rfovfie rq vfie rqltie rqhtie default 0 0 0 0 0 0 0 0 bit 3: receive fifo overflow interrupt enable (rfovfie) if this bit is set, the interrupt is enabled for rfovfls. bit 2: receive queue overflow interrupt enable (rqvfie) if this bit is set, the interrupt is enabled for rqovfls. bit 1: receive queue crosses low threshold interrupt enable (rqltie) if this bit is set, the watermark interrupt is enabled for rqlts. bit 0: receive queue crosses high threshold interrupt enable (rqhtie) if this bit is set, the watermark interrupt is enabled for rqhts. register name: su.qcrls register description: queue cross threshold latched status register address: 15dh bit # 7 6 5 4 3 2 1 0 name - - - - rfovfls r qovfls rqhtls rqltls default - - - - - - - - bit 3: receive fifo overflow latched status (rfovfls) this bit is set if the receive fifo overflows for the data to be transmitted from the mac to the sdram. bit 2: receive queue overflow latched status (rqovfls) this bit is set if the receive queue has overflowed. this register is cleared after a read. bit 1: receive queue for c onnection crossed high threshol d latched status (rqhtls) this bit is set if the receive queue crosses the high watermark. this register is cleared after a read. bit 0: receive queue for c onnection crossed low threshol d latched status (rqltls) this bit is set if the receive queue crosses the low watermark. this register is cleared after a read. note the bit order differences in the high/low thres hold indications in su.qcrls and the interrupt enables in su.qrie.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 181 of 338 register name: su.rfrc register description: receive frame rejection control register address: 15eh bit # 7 6 5 4 3 2 1 0 name - ucfr cfrr lerr crcerr dbr miier bfr default 0 0 0 0 0 0 0 0 bit 6: uncontrolled contro l frame reject (ucfr) when set to 1, control frames other than pause frames are allowed. when this bit is equal to zero, nonpause control frames are rejected. bit 5: control frame reject (cfrr) when set to 1, control frames are allowed. when this bit is equal to zero, all control frames are rejected. bit 4: length error reject (lerr) when set to 1, frames with an unmatched frame length field and actual number of bytes received are allowed. when equal to zero, only frames with matching length fields and actual bytes received will be allowed. bit 3: crc error reject (crcerr) when set to 1, frames received with a crc error or mii error are allowed. when equal to zero, frames with crc or mii errors are rejected. bit 2: dribbling bit reject (dbr) when set to 1, frames with lengths of noninteger multiples of 8 bits are allowed. when equal to zero, frames with dribbling bits are rejected. the dribbling bit setting is only valid only if there is not a collision or runt frame. bit 1: mii error reject (miier) when set to 1, frames are allowed with mii receive errors. when equal to zero, frames with mii errors are rejected. bit 0: broadcast frame reject (bfr) when set to 1, broadcast frames are allowed. when equal to zero, broadcast frames are rejected.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 182 of 338 11.6.2 mac registers the control registers related to the control of the individual mac?s are shown in the following table. the DS33R11 keeps statistics for the packet traffic sent and received. the register address map is shown in the following table. note that the addresses listed are the indirect addresses that must be provided to su.macradh / su.macradl or su.macawh / su.macawl . register name: su.maccr register description: mac control register register address: 0000h (indirect) 0000h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved hdb ps reserved reserved reserved default 0 0 0 0 0 0 0 0 0001h: bit # 23 22 21 20 19 18 17 16 name dro reserved oml0 f reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0002h: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved lcc reserved drty reserved astp default 0 0 0 0 0 0 0 0 0003h: bit # 07 06 05 04 03 02 01 00 name bolmt1 bolmt0 dc reserved te re reserved reserved default 0 0 0 0 0 0 0 0 bit 28: heartbeat disable (hdb) when set to 1, the heartbeat (sqe) function is disabled. this bit should be set to 1 when operating in mii mode. bit 27: port select (ps) this bit should be equal to 0 for proper operation. bit 23: disable receive own (dro) when set to 1, the mac disables the reception of frames while tx_en is asserted. when this bit equals zero, transmitted frames ar e also received by the mac. this bit should be cleared when operating in full-duplex mode. bit 21: loopback operating mode (omlo) when set to 1, data is looped from the transmit side, back to the receive side, without being transmitted to the phy. bit 20: full-duplex mode select (f) when set to 1, the mac transmits and receives data simultaneously. when in full-duplex mode, the heartbeat check is disabled and the heartbeat fail status should be ignored.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 183 of 338 bit 12: late collision control (lcc) when set to 1, enables retransmission of a collided packet even after the collision period. when this bit is clear, retransmission of late collisions is disabled. bit 10: disable retry (drty) when set to 1, the mac makes only a single attempt to transmit each frame. if a collision occurs, the mac ignores the current frame and proceeds to the next frame. when this bit equals 0, the mac will retry collided packets 16 times before signaling a retry error. bit 8: automatic pad stripping (astp) when set to 1, all incoming frames with less than 46 byte length are automatically stripped of the pad characters and fcs. bits 6 - 7: back-off limit (bolmt[0:1]) these two bits allow the user to set the back-off limit used for the maximum retransmission delay for collided packets. default operation limits the maximum delay for retransmission to a countdown of 10 bits from a random number generator. the user can reduce the maximum number of counter bits as described in the table below. see ieee 802.3 for details of the back-off algorithm. bit 7 bit 6 random number generator bits used 0 0 10 0 1 8 1 0 4 1 1 1 bit 5: deferral check (dc) when set to 1, the mac will abort packet transmission if it has deferred for more than 24,288 bit times. the deferral counter starts when the transmitter is ready to transmit a packet, but is prevented from transmission because crs is active. if the mac begi ns transmission but a collision occurs after the beginning of transmission, the deferral counter is reset again. if this bit is equal to zero, then the mac will defer indefinitely. bit 3: transmitter enable (te) when set to 1, packet transmission is enabled. when equal to zero, transmission is disabled. bit 2: receiver enable (re) when set to 1, packet reception is enabled. when equal to zero, packets are not received.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 184 of 338 register name: su.macmiia register description: mac mii management (mdio) address register register address: 0014h (indirect) 0014h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0015h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0016h: bit # 15 14 13 12 11 10 09 08 name phya4 phya3 phya2 phya1 phya0 miia4 miia3 miia2 default 0 1 0 1 1 0 1 0 0017h: bit # 07 06 05 04 03 02 01 00 name miia1 miia0 reserved reserved reserved reserved miiw miib default 1 1 0 0 0 0 0 0 bits 11 - 15: phy address (phya[0:4]) these 5 bits select one of the 32 available phy address locations to access through the phy management (mdio) bus. bits 6 - 10: mii address (miia[0:4]) - these 5 bits are the address location within the phy that is being accessed. bit 1: mii write (miiw) write this bit to 1 in order to execute a write instruction over the mdio interface. write the bit to zero to execute a read instruction. bit 0: mii busy (miib) this bit is set to 1 by the DS33R11 during execution of a mii management instruction through the mdio interface, and is set to zero when the DS33R11 has completed the instruction. the user should read this bit and ensure that it is equal to zero prior to beginning a mdio instruction.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 185 of 338 register name: su.macmiid register description: mac mii (mdio) data register register address: 0018h (indirect) 0018h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0019h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 001ah: bit # 15 14 13 12 11 10 09 08 name miid15 miid14 miid13 miid12 miid11 miid10 miid09 miid08 default 0 0 0 0 0 0 0 0 001bh: bit # 07 06 05 04 03 02 01 00 name miid07 miid06 miid05 miid04 miid03 miid02 miid01 miid00 default 0 0 0 0 0 0 0 0 bits 0 ? 15: mii (mdio) data (miid[00:15]) these two bytes contain the data to be written to or the data read from the mii management interface (mdio).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 186 of 338 register name: su.macfcr register description: mac flow control register register address: 001ch (indirect) 001ch: bit # 31 30 29 28 27 26 25 24 name pt15 pt14 pt13 pt12 pt11 pt10 pt09 pt08 default 0 0 0 0 0 0 0 0 001dh: bit # 23 22 21 20 19 18 17 16 name pt07 pt06 pt05 pt04 pt03 pt02 pt01 pt00 default 0 1 0 1 0 0 0 0 001eh: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 001fh: bit # 07 06 05 04 03 02 01 00 name reserved reserved reserved reserved reserved reserved fce fcb default 0 0 0 0 0 0 1 0 bits 16 - 31: pause time (pt[00:15]) these bits are used for the pause time field in transmitted pause frames. this value is the number of time slots the remote node should wait prior to transmission. bit 1: flow control enable (fce) when set to 1, the mac automatically detects pause frames and will disable the transmitter for the requested pause time. bit 0: flow control busy (fcb) the host can set this bit to 1 in order to initiate transmission of a pause frame. during transmission of a pause frame, this bit remains set. the DS33R11 will clear this bit when transmission of the pause frame has been completed. the user should read this bit and ensure that this bit is equal to zero prior to initiating a pause frame.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 187 of 338 register name: su.mmcctrl register description: mac mmc control register register address: 0100h (indirect) 0100h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0101h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0102h: bit # 15 14 13 12 11 10 09 08 name reserved reserved mxfrm10 mxfrm9 mxfrm8 mxfrm7 mxfrm6 mxfrm5 default 0 0 1 0 1 1 1 1 0103h: bit # 07 06 05 04 03 02 01 00 name mxfrm4 mxfrm3 mxfrm2 mxfrm1 mxfrm0 reserved reserved reserved default 0 1 1 1 0 0 1 0 bits 3 - 13: maximum frame size (mxfrm[0:10]) these bits indicate the maximum packet size value. all transmitted frames larger than this value are counted as long frames. bit 1: reserved - note that this bit must be written to a ?1? for proper operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 188 of 338 register name: reserved register description: mac reserved control register register address: 010ch (indirect) 010ch: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 010dh: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 010eh: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 010fh: bit # 07 06 05 04 03 02 01 00 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 note ? addresses 10ch through 10fh must each be initialized with all 1? s (ffh) for proper software-mode operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 189 of 338 register name: reserved register description: mac reserved control register register address: 0110h (indirect) 0110h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0111h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0112h: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0113h: bit # 07 06 05 04 03 02 01 00 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 note ? addresses 110h through 113h must each be initialized with all 1? s (ffh) for proper software-mode operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 190 of 338 register name: su.rxfrmctr register description: mac all frames received counter register address: 0200h (indirect) 0200h: bit # 31 30 29 28 27 26 25 24 name rxfrmc31 rxfrmc30 rxfrmc29 rxfrmc28 rxfrmc27 rxfrmc26 rxfrmc25 rxfrmc24 default 0 0 0 0 0 0 0 0 0201h: bit # 23 22 21 20 19 18 17 16 name rxfrmc23 rxfrmc22 rxfrmc21 rxfrmc20 rxfrmc19 rxfrmc18 rxfrmc17 rxfrmc16 default 0 0 0 0 0 0 0 0 0202h: bit # 15 14 13 12 11 10 09 08 name rxfrmc15 rxfrmc14 rxfrmc13 rxfrmc12 rxfrmc11 rxfrmc10 rxfrmc9 rxfrmc8 default 0 0 0 0 0 0 0 0 0203h: bit # 07 06 05 04 03 02 01 00 name rxfrmc7 rxfrmc6 rxfrmc5 rxfrmc4 rxfrmc3 rxfrmc2 rxfrmc1 rxfrmc0 default 0 0 0 0 0 0 0 0 bits 0 - 31: all frames received counter (rxfrmc[0:31]) 32 bit value indicating the number of frames received. each time a frame is received, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 191 of 338 register name: su.rxfrmokctr register description: mac frames received ok counter register address: 0204h (indirect) 0204h: bit # 31 30 29 28 27 26 25 24 name rxfrmok31 rxfrmok30 rxfrmok29 rxfrmok28 rxfrmok27 rxfrmok26 rxfrmok25 rxfrmok24 default 0 0 0 0 0 0 0 0 0205h: bit # 23 22 21 20 19 18 17 16 name rxfrmok23 rxfrmok22 rxfrmok21 rxfrmok20 rxfrmok19 rxfrmok18 rxfrmok17 rxfrmok16 default 0 0 0 0 0 0 0 0 0206h: bit # 15 14 13 12 11 10 09 08 name rxfrmok15 rxfrmok14 rxfrmok13 rxfrmok12 rxfrmok11 rxfrmok10 rxfrmok9 rxfrmok8 default 0 0 0 0 0 0 0 0 0207h: bit # 07 06 05 04 03 02 01 00 name rxfrmok7 rxfrmok6 rxfrmok5 rxfrmok4 rxfrmok3 rxfrmok2 rxfrmok1 rxfrmok0 default 0 0 0 0 0 0 0 0 bits 0 - 31: frames received ok counter (rxfrmok[0:31]) 32 bit value indicating the number of frames received and determined to be valid. each time a valid frame is received, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 192 of 338 register name: su.txfrmctr register description: mac all frames transmitted counter register address: 0300h (indirect) 0300h: bit # 31 30 29 28 27 26 25 24 name txfrmc31 txfrmc30 txfrmc29 txfrmc28 txfrmc27 txfrmc26 txfrmc25 txfrmc24 default 0 0 0 0 0 0 0 0 0301h: bit # 23 22 21 20 19 18 17 16 name txfrmc23 txfrmc22 txfrmc21 txfrmc20 txfrmc19 txfrmc18 txfrmc17 txfrmc16 default 0 0 0 0 0 0 0 0 0302h: bit # 15 14 13 12 11 10 09 08 name txfrmc15 txfrmc14 txfrmc13 txfrmc12 txfrmc11 txfrmc10 txfrmc9 txfrmc8 default 0 0 0 0 0 0 0 0 0303h: bit # 07 06 05 04 03 02 01 00 name txfrmc7 txfrmc6 txfrmc5 txfrmc4 txfrmc3 txfrmc2 txfrmc1 txfrmc0 default 0 0 0 0 0 0 0 0 bits 0 - 31: all frames transmitted counter (txfrmc[0:31]) 32 bit value indicating the number of frames transmitted. each time a frame is transmitted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 193 of 338 register name: su.txbytesctr register description: mac all bytes transmitted counter register address: 0308h (indirect) 0308h: bit # 31 30 29 28 27 26 25 24 name txbytec31 txbytec30 txbytec29 txbytec28 txbytec27 txbytec26 txbytec25 txbytec24 default 0 0 0 0 0 0 0 0 0309h: bit # 23 22 21 20 19 18 17 16 name txbytec23 txbytec22 txbytec21 txbytec20 txbytec19 txbytec18 txbytec17 txbytec16 default 0 0 0 0 0 0 0 0 030ah: bit # 15 14 13 12 11 10 09 08 name txbytec15 txbytec14 txbytec13 txbytec12 txbytec11 txbytec10 txbytec9 txbytec8 default 0 0 0 0 0 0 0 0 030bh: bit # 07 06 05 04 03 02 01 00 name txbytec7 txbytec6 txbytec5 txbytec4 txbytec3 txbytec2 txbytec1 txbytec0 default 0 0 0 0 0 0 0 0 bits 0 - 31: all bytes transmitted counter (txbytec[0:31]) 32 bit value indicating the number of bytes transmitted. each time a byte is transmitted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum data rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 194 of 338 register name: su.txbytesokctr register description: mac bytes transmitted ok counter register address: 030ch (indirect) 030ch: bit # 31 30 29 28 27 26 25 24 name txbyteok31 txbyteok30 txbyteok29 txbyteok28 txbyteok27 txbyteok26 txbyteok25 txbyteok24 default 0 0 0 0 0 0 0 0 030dh: bit # 23 22 21 20 19 18 17 16 name txbyteok23 txbyteok22 txbyteok21 txbyteok20 txbyteok19 txbyteok18 txbyteok17 txbyteok16 default 0 0 0 0 0 0 0 0 030eh: bit # 15 14 13 12 11 10 09 08 name txbyteok15 txbyteok14 txbyteok13 txbyteok12 txbyteok11 txbyteok10 txbyteok9 txbyteok8 default 0 0 0 0 0 0 0 0 030fh: bit # 07 06 05 04 03 02 01 00 name txbyteok7 txbyteok6 txbyteok5 txbyteok4 txbyteok3 txbyteok2 txbyteok1 txbyteok0 default 0 0 0 0 0 0 0 0 bits 0 - 31: bytes transmitted ok counter (txbyteok[0:31]) 32 bit value indicating the number of bytes transmitted and determined to be valid. each time a valid byte is transmitted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 195 of 338 register name: su.txfrmundr register description: mac transmit frame under run counter register address: 0334h (indirect) 0334h: bit # 31 30 29 28 27 26 25 24 name txfrmu31 txfrmu30 txfrmu29 txfrmu28 txfrmu27 txfrmu26 txfrmu25 txfrmu24 default 0 0 0 0 0 0 0 0 0335h: bit # 23 22 21 20 19 18 17 16 name txfrmu23 txfrmu22 txfrmu21 txfrmu20 txfrmu19 txfrmu18 txfrmu17 txfrmu16 default 0 0 0 0 0 0 0 0 0336h: bit # 15 14 13 12 11 10 09 08 name txfrmu15 txfrmu14 txfrmu13 txfrmu12 txfrmu11 txfrmu10 txfrmu9 txfrmu8 default 0 0 0 0 0 0 0 0 0337h: bit # 07 06 05 04 03 02 01 00 name txfrmu7 txfrmu6 txfrmu5 txfrmu4 txfrmu3 txfrmu2 txfrmu1 txfrmu0 default 0 0 0 0 0 0 0 0 bits 0 - 31: frames aborted due to fifo under run counter (txfrmu[0:31]) 32 bit value indicating the number of frames aborted due to fifo under run. each time a frame is aborted due to fifo under run, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 196 of 338 register name: su.txbdfrmctr register description: mac all frames aborted counter register address: 0338h (indirect) 0338h: bit # 31 30 29 28 27 26 25 24 name txfrmbd31 txfrmbd30 txfrmbd29 txfrmbd28 txfrmbd27 txfrmbd26 txfrmbd25 txfrmbd24 default 0 0 0 0 0 0 0 0 0339h: bit # 23 22 21 20 19 18 17 16 name txfrmbd23 txfrmbd22 txfrmbd21 txfrmbd20 txfrmbd19 txfrmbd18 txfrmbd17 txfrmbd16 default 0 0 0 0 0 0 0 0 033ah: bit # 15 14 13 12 11 10 09 08 name txfrmbd15 txfrmbd14 txfrmbd13 txfrmbd12 txfrmbd11 txfrmbd10 txfrmbd9 txfrmbd8 default 0 0 0 0 0 0 0 0 033bh: bit # 07 06 05 04 03 02 01 00 name txfrmbd7 txfrmbd6 txfrmbd5 txfrmbd4 txfrmbd3 txfrmbd2 txfrmbd1 txfrmbd0 default 0 0 0 0 0 0 0 0 bits 0 to 31: all frames aborted counter (txfrmbd[0:31]) 32 bit value indicating the number of frames aborted due to any reason. each time a frame is aborted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 197 of 338 11.7 t1/e1/j1 transceiver registers register name: tr.mstrreg register description: master mode register register address: 00h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? test1 test0 t1/e1 sftrst default 0 0 0 0 0 0 0 0 bits 2 ? 3: test mode bits (test0, test1) test modes are used to force the output pins of the transceiver into known states. this can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses. test1 test0 effect on output pins 0 0 operate normally 0 1 force all output pins into tri-state (including all i/o pins and parallel port pins) 1 0 force all output pins low (including all i/o pins except parallel port pins) 1 1 force all output pins high (including all i/o pins except parallel port pins) bit 1: transceiver operating mode (t1/e1) used to select the operating mode of the framer/formatter (digital) portion of the transceiver. the operating mode of the liu must also be programmed. 0 = t1 operation 1 = e1 operation bit 0: software-issued reset (sftrst) a 0-to-1 transition causes the register space in the t1/e1/j1 transceiver to be cleared. a reset clears all configuration and status registers. the bit automatically clears itself when the reset has completed.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 198 of 338 register name: tr.iocr1 register description: i/o configuration register 1 register address: 01h bit # 7 6 5 4 3 2 1 0 name rsms rsms2 rsms1 rs io tsdw tsm tsio odf default 0 0 0 0 0 0 0 0 bit 7: rsync multiframe skip control (rsms) useful in framing format conversions from d4 to esf. this function is not available when the receive-side elastic st ore is enabled. rsync must be set to output multiframe pulses (tr.iocr1.5 = 1 and tr.iocr1.4 = 0). 0 = rsync outputs a pulse at every multiframe 1 = rsync outputs a pulse at every other multiframe bit 6: rsync mode select 2 (rsms2) t1 mode: rsync pin must be programmed in the output frame mode (tr.iocr1.5 = 0,tr.iocr1.4 = 0). 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames e1 mode: rsync pin must be programmed in the output multiframe mode (tr.iocr1.5 = 1, tr.iocr1.4 = 0). 0 = rsync outputs cas multiframe boundaries 1 = rsync outputs crc4 multiframe boundaries bit 5: rsync mode select 1(rsms1) selects frame or multiframe pulse when rsync pin is in output mode. in input mode (elastic store must be enabled), multiframe mode is only useful when receive signaling reinsertion is enabled. see the timing diagrams in section 12 . 0 = frame mode 1 = multiframe mode bit 4: rsync i/o select (rsio) (note: this bit must be set to 0 when tr.escr.0 = 0.) 0 = rsync is an output 1 = rsync is an input (only valid if elastic store enabled) bit 3: tsync double-wide (tsdw) (note: this bit must be set to 0 when tr.iocr1.2 = 1 or when tr.iocr1.1 = 0.) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames bit 2: tsync mode select (tsm) selects frame or multiframe mode for the tsync pin. see the timing diagrams in section 12 . 0 = frame mode 1 = multiframe mode bit 1: tsync i/o select (tsio) 0 = tsync is an input 1 = tsync is an output bit 0: output data format (odf) 0 = bipolar data at tposo and tnego 1 = nrz data at tposo; tnego = 0
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 199 of 338 register name: tr.iocr2 register description: i/o configuration register 2 register address: 02h bit # 7 6 5 4 3 2 1 0 name rclkinv tclkinv rsyncinv tsynci nv tssyncinv h100en tsclkm rsclkm default 0 0 0 0 0 0 0 0 bit 7: rclko invert (rclkinv) 0 = no inversion 1 = inverts signal on rclko output. bit 6: tclkt invert (tclkinv) 0 = no inversion 1 = inverts signal on tclkt input. bit 5: rsync invert (rsyncinv) 0 = no inversion 1 = invert bit 4: tsync invert (tsyncinv) 0 = no inversion 1 = invert bit 3: tssync invert (tssyncinv) 0 = no inversion 1 = invert bit 2 : h.100 sync mode (h100en) 0 = normal operation 1 = sync shift bit 1: tsysclk mode select (tsclkm) 0 = if tsysclk is 1.544mhz 1 = if tsysclk is 2.048mhz bit 0: rsysclk mode select (rsclkm) 0 = if rsysclk is 1.544mhz 1 = if rsysclk is 2.048mhz
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 200 of 338 register name: tr.t1rcr1 register description: t1 receive control register 1 register address: 03h bit # 7 6 5 4 3 2 1 0 name ? arc oof1 oof2 syncc synct synce resync default 0 0 0 0 0 0 0 0 bit 6: auto resync criteria (arc) 0 = resync on oof or rcl event 1 = resync on oof only bits 4- 5: out-of-frame select bits (oof2, oof1) oof2 oof1 out-of-frame criteria 0 0 2/4 frame bits in error 0 1 2/5 frame bits in error 1 0 2/6 frame bits in error 1 1 2/6 frame bits in error bit 3: sync criteria (syncc) in d4 framing mode: 0 = search for ft pattern, then search for fs pattern 1 = cross couple ft and fs pattern in esf framing mode: 0 = search for fps pattern only 1 = search for fps and verify with crc6 bit 2: sync time (synct) 0 = qualify 10 bits 1 = qualify 24 bits bit 1: sync enable (synce) 0 = auto resync enabled 1 = auto resync disabled bit 0: resynchronize (resync) when toggled from low to high, a resynchronization of the receive-side framer is initiated. must be cleared and set again for a subsequent resync.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 201 of 338 register name: tr.t1rcr2 register description: t1 receive control register 2 register address: 04h bit # 7 6 5 4 3 2 1 0 name ? rfm rb8zs rslc96 rzse ? rjc rd4ym default 0 0 0 0 0 0 0 0 bit 6: receive frame mode select (rfm) 0 = d4 framing mode 1 = esf framing mode bit 5: receive b8zs enable (rb8zs) 0 = b8zs disabled 1 = b8zs enabled bit 4: receive slc-96 enable (rslc96). only set this bit to a 1 in d4/slc-96 framing applications. see section 10.19 for details. 0 = slc-96 disabled 1 = slc-96 enabled bit 3: receive fdl zero-destuffer enable (rzse). set this bit to 0 if using the internal hdlc/boc controller instead of the legacy support for the fdl. see section 10.18 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled bit 2: reserved. set to zero for proper operation. bit 1: receive japan ese crc6 enable (rjc) 0 = use ansi/at&t/itu crc6 ca lculation (nor mal operation) 1 = use japanese standard jt?g704 crc6 calculation bit 0: receive-side d4 yellow alarm select (rd4ym) 0 = 0s in bit 2 of all channels 1 = a 1 in the s-bit position of frame 12 (j1 yellow alarm mode)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 202 of 338 register name: tr.t1tcr1 register description: t1 transmit control register 1 register address: 05h bit # 7 6 5 4 3 2 1 0 name tjc tfpt tcpt tsse gb7s tfdls tbl tyel default 0 0 0 0 0 0 0 0 bit 7: transmit japan ese crc6 enable (tjc) 0 = use ansi/at&t/itu crc6 ca lculation (nor mal operation) 1 = use japanese standard jt?g704 crc6 calculation bit 6: transmit f-bit pass-through (tfpt) 0 = f bits sourced internally 1 = f bits sampled at tseri bit 5: transmit crc pass-through (tcpt) 0 = source crc6 bits internally 1 = crc6 bits sampled at tseri during f-bit time bit 4: transmit software signaling enable (tsse). 0 = do not source signaling data from the tr.tsx registers regardless of the tr.ssiex registers. the tr.ssiex registers still define which channels are to have b7 stuffing preformed. 1 = source signaling data as enabled by the tr.ssiex registers bit 3: global bit 7 stuffing (gb7s) 0 = allow the ssiex registers to determine which channels containing all 0s are to be bit 7 stuffed 1 = force bit 7 stuffing in all 0-byte channels regardless of how the tr.ssiex registers are programmed bit 2: tfdl register select (tfdls) 0 = source fdl or fs-bits from the internal tr.tfdl register (legacy fdl support mode) 1 = source fdl or fs-bits from the internal hdlc controller bit 1: transmit blue alarm (tbl) 0 = transmit data normally 1 = transmit an unframed all-ones code at tpos and tneg bit 0: transmit yellow alarm (tyel) 0 = do not transmit yellow alarm 1 = transmit yellow alarm
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 203 of 338 register name: tr.t1tcr2 register description: t1 transmit control register 2 register address: 06h bit # 7 6 5 4 3 2 1 0 name tb8zs tslc96 tzse fbct2 fbct1 td4ym ? tb7zs default 0 0 0 0 0 0 0 0 bit 7: transmit b8zs enable (tb8zs) 0 = b8zs disabled 1 = b8zs enabled bit 6: transmit slc-96/fs-bit insertion enable (tslc96). only set this bit to a 1 in d4 framing applications. must be set to 1 to source the fs pattern from the tr.tfdl register. see section 10.19 for details. 0 = slc-96/fs-bit insertion disabled 1 = slc-96/fs-bit insertion enabled bit 5: transmit fdl zero-stuffer enable (tzse). set this bit to 0 if using the internal hdlc controller instead of the legacy support for the fdl. see section 15 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled bit 4: f-bit corruption type 2 (fbct2). setting this bit high enables the corruption of one ft (d4 framing mode) or fps (esf framing mode) bit in every 128 ft or fps bits as long as the bit remains set. bit 3: f-bit corruption type 1 (fbct1). a low-to-high transition of this bit causes the next three consecutive ft (d4 framing mode) or fps (esf framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization. bit 2: transmit-side d4 yellow alarm select (td4ym) 0 = 0s in bit 2 of all channels 1 = a 1 in the s-bit position of frame 12 bit 0: transmit-side bit 7 zero-suppression enable (tb7zs) 0 = no stuffing occurs 1 = bit 7 forced to a 1 in channels with all 0s
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 204 of 338 register name: tr.t1ccr1 register description: t1 common control register 1 register address: 07h bit # 7 6 5 4 3 2 1 0 name ? ? ? trai-ci tais-ci tfm pde tloop default 0 0 0 0 0 0 0 0 bit 4: transmit rai-ci enable (trai-ci). setting this bit causes the esf rai-ci code to be transmitted in the fdl bit position. 0 = do not transmit the esf rai-ci code 1 = transmit the esf rai-ci code bit 3: transmit ais-ci enable (tais-ci). setting this bit and the tbl bit (tr.t1tcr1.1) causes the ais-ci code to be transmitted at tposo and tnego, as defined in ansi t1.403. 0 = do not transmit the ais-ci code 1 = transmit the ais-ci code (tr.t1tcr1.1 must also be set = 1) bit 2: transmit frame mode select (tfm) 0 = d4 framing mode 1 = esf framing mode bit 1: pulse density enforcer enable (pde). the framer always examines the transmit and receive data streams for violations of these, which are required by ansi t1.403: no more than 15 consecutive 0s and at least n 1s in each and every time window of 8 x (n + 1) bits, where n = 1 through 23. violations for the transmit and receive data streams are reported in the tr.info1.6 and tr.info1.7 bits, respectively. when this bit is set to 1, the t1/e1/j1 transceiver forces the transmitted stream to meet this requirement no matter the content of the transmitted stream. when running b8zs, this bit should be set to 0 since b8zs encoded data streams cannot violate the pulse density requirements. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer bit 0: transmit loop-code enable (tloop). see section 10.20 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers tr.tcd1 and tr.tcd2 register name: tr.ssie1 (t1 mode) register description: software signaling insertion enable 1 register address: 08h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 ? 7: software signaling insertion enable for channels 1 to 8 (ch1 to ch8). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tr.tsx registers for this channel 1 = source signaling data from the tr.tsx registers for this channel
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 205 of 338 register name: tr.ssie1 (e1 mode) register description: software signaling insertion enable 1 register address: 08h bit # 7 6 5 4 3 2 1 0 name ch7 ch6 ch5 ch4 ch3 ch2 ch1 ucaw default 0 0 0 0 0 0 0 0 bits 1 ? 7: software signaling-insertion enable for channels 1 to 7 (ch1 to ch7). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tr.tsx registers for this channel 1 = source signaling data from the tr.tsx registers for this channel bit 0: upper cas align/alarm word (ucaw). selects the upper cas align/alarm pattern (0000) to be sourced from the upper 4 bits of the ts1 register. 0 = do not source the upper cas align/alarm pattern from the tr.ts1 register 1 = source the upper cas align/alarm pattern from the tr.ts1 register register name: tr.ssie2 (t1 mode) register description: software signaling-insertion enable 2 register address: 09h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 ? 7: software signaling insertion enable for channels 9 to 16 (ch9 to ch16). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tr.tsx registers for this channel 1 = source signaling data from the tr.tsx registers for this channel register name: tr.ssie2 (e1 mode) register description: software signaling insertion enable 2 register address: 09h bit # 7 6 5 4 3 2 1 0 name ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: software signaling insertion enable for channels 8 to 15 (ch8 to ch15). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tr.tsx registers for this channel 1 = source signaling data from the tr.tsx registers for this channel
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 206 of 338 register name: tr.ssie3 (t1 mode) register description: software signaling-insertion enable 3 register address: 0ah bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 ? 7: software signaling insertion enable for channels 17 to 24 (ch17 to ch24). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tr.tsx registers for this channel 1 = source signaling data from the tr.tsx registers for this channel register name: tr.ssie3 (e1 mode) register description: software signaling insertion enable 3 register address: 0ah bit # 7 6 5 4 3 2 1 0 name ch22 ch21 ch20 ch19 ch18 ch17 ch16 lcaw default 0 0 0 0 0 0 0 0 bits 1 ? 7: software signaling insertion enable for lcaw and channels 16 to 22 (ch16 to ch22). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tr.tsx registers for this channel 1 = source signaling data from the tr.tsx registers for this channel bit 0: lower cas align/alarm word (lcaw). selects the lower cas align/alarm bits (xyxx) to be sourced from the lower 4 bits of the ts1 register. 0 = do not source the lower cas align/alarm bits from the tr.ts1 register 1 = source the lower cas alarm align/bits from the tr.ts1 register register name: tr.ssie4 register description: software signaling insertion enable 4 register address: 0bh bit # 7 6 5 4 3 2 1 0 name ch30 ch29 ch28 ch27 ch26 ch25 ch24 ch23 default 0 0 0 0 0 0 0 0 bits 0 ? 7: software signaling insertion enable for channels 22 to 30 (ch23 to ch30). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tr.tsx registers for this channel 1 = source signaling data from the tr.tsx registers for this channel
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 207 of 338 register name: tr.t1rdmr1 register description: t1 receive digital-milliwatt enable register 1 register address: 0ch bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive digital-milliwatt enable for channels 1 to 8 (ch1 to ch8) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code register name: tr.t1rdmr2 register description: t1 receive digital-milliwatt enable register 2 register address: 0dh bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive digital-milliwatt enable for channels 9 to 16 (ch9 to ch16) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code register name: tr.t1rdmr3 register description: t1 receive digital-milliwatt enable register 3 register address: 0eh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive digital-milliwatt enable for channels 17 to 24 (ch17 to ch24) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 208 of 338 register name: tr.idr register description: device identification register register address: 0fh bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 default 1 0 1 1 x x x x bits 4 - 7: device id (id4 to id7). the upper four bits of tr.idr are used to display the transceiver id. bits 0 ? 3: chip revision bits (id0 to id3). the lower four bits of tr.idr are used to display the die revision of the chip. ido is the lsb of a decimal code that represents the chip revision. register name: tr.info1 register description: information register 1 register address: 10h bit # 7 6 5 4 3 2 1 0 name rpdv tpdv cofa 8zd 16zd sefe b8zs fbe default 0 0 0 0 0 0 0 0 bit 7: receive pulse-density violation event (rpdv). set when the receive data stream does not meet the ansi t1.403 requirements for pulse density. bit 6: transmit pulse-density violation event (tpdv). set when the transmit data stream does not meet the ansi t1.403 requirements for pulse density. bit 5: change-of-frame alignment event (cofa). set when the last resync resulted in a change-of-frame or multiframe alignment. bit 4: eight zero-detect event (8zd). set when a string of at least eight consecutive 0s (regardless of the length of the string) have been received at rposi and rnegi. bit 3: sixteen zero-detect event (16zd). set when a string of at least 16 consecutive 0s (regardless of the length of the string) have been received at rposi and rnegi. bit 2: severely errored framing event (sefe). set when two out of six framing bits (ft or fps) are received in error. bit 1: b8zs codeword detect event (b8zs). set when a b8zs codeword is detected at rpos and rneg independent of whether the b8zs mode is selected or not by tr.t1tcr2.7. useful for automatically setting the line coding. bit 0: frame bit-error event (fbe). set when an ft (d4) or fps (esf) framing bit is received in error.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 209 of 338 register name: tr.info2 register description: information register 2 register address: 11h bit # 7 6 5 4 3 2 1 0 name bsync bd tcle tocd rl3 rl2 rl1 rl0 default 0 0 0 0 0 0 0 0 bit 7: bert real-time synchronization status (bsync). real-time status of the synchronizer (this bit is not latched). this bit is set when the incoming pattern matches for 32 consecutive bit positions. it is cleared when six or more bits out of 64 are received in error. refer to bsync in the bert status register, tr.sr9, for an interrupt- generating version of this signal. bit 6: boc detected (bd). a real-time bit that is set high when the boc detector is presently seeing a valid sequence and set low when no boc is currently being detected. bit 5: transmit current-limit exceeded (tcle). a real-time bit that is set when the 50ma (rms) current limiter is activated, whether the current limiter is enabled or not. bit 4: transmit open-circuit detect (tocd). a real-time bit that is set when the device detects that the ttip and tring outputs are open-circuited. bits 0 ? 3: receive level bits (rl0 to rl3). real-time bits rl3 rl2 rl1 rl0 receive level (db) 0 0 0 0 greater than -2.5 0 0 0 1 -2.5 to -5.0 0 0 1 0 -5.0 to -7.5 0 0 1 1 -7.5 to -10.0 0 1 0 0 -10.0 to -12.5 0 1 0 1 -12.5 to -15.0 0 1 1 0 -15.0 to -17.5 0 1 1 1 -17.5 to -20.0 1 0 0 0 -20.0 to -22.5 1 0 0 1 -22.5 to -25.0 1 0 1 0 -25.0 to -27.5 1 0 1 1 -27.5 to -30.0 1 1 0 0 -30.0 to -32.5 1 1 0 1 -32.5 to -35.0 1 1 1 0 -35.0 to -37.5 1 1 1 1 less than -37.5 note: rl0 through rl3 only indicate the signal range as spec ified by the egl bit in tr.lic1. example; if egl = 1 and in t1 mode, rl0 through rl3 will only indicate a signal range of >-2.5db to ?15db even if the signal is < -15db.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 210 of 338 register name: tr.info3 register description: information register 3 register address: 12h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? crcrc fasrc casrc default 0 0 0 0 0 0 0 0 bit 2: crc resync criteria met event (crcrc). set when 915/1000 codewords are received in error. bit 1: fas resync criteria met event (fasrc). set when three consecutive fas words are received in error. note: during a crc resync the fas synchronizer is brought online to verify the fas alignment. if during this process an fas emulator exists, the fas synchronizer may temporarily align to the emulator. the fasrc will go active indicating a search for a valid fas has been activated. bit 0: cas resync criteria met event (casrc). set when two consecutive cas mf alignment words are received in error. register name: tr.iir1 register description: interrupt information register 1 register address: 14h bit # 7 6 5 4 3 2 1 0 name sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 default 0 0 0 0 0 0 0 0 bits 0 ? 7: status register 1 ? 8 when set to 1, these bits indicate that an enabled interrupt is active in the associated t1/e1/j1 status register. register name: tr.iir2 register description: interrupt information register 2 register address: 15h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? sr9 default 0 0 0 0 0 0 0 0 bits 0: status register 9 when set to 1, this bit indicates that an enabled interrupt is active in the associated t1/e1/j1 status register.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 211 of 338 register name: tr.sr1 register description: status register 1 register address: 16h bit # 7 6 5 4 3 2 1 0 name ilut timer rscos jalt lrcl tcle tocd lolitc default 0 0 0 0 0 0 0 0 bit 7: input level under threshold (ilut). this bit is set whenever the input level at rtip and rring falls below the threshold set by the value in tr.ccr4.4 through tr .ccr4.7. the level must remain below the programmed threshold for approximately 50ms for this bit to be set. this is a double interrupt bit (section 9.7 ). bit 6: timer event (timer). follows the error-counter update interval as determined by the ecus bit in the error- counter configuration register (tr.ercnt). t1: set on increments of 1 second or 42ms based on rclko e1: set on increments of 1 second or 62.5ms based on rclko bit 5: receive signaling change-of-state event (rscos). set when any channel selected by the receive signaling change-of-state interrupt-enable registers (tr.rscse1 through tr.rscse4) changes signaling state. bit 4: jitter attenuator limit trip event (jalt). set when the jitter attenuator fifo reaches to within 4 bits of its useful limit. this bit is cleared when read. us eful for debugging jitter attenuation operation. bit 3: line interface receive carrier-loss condition (lrcl). set when the carrier signal is lost. this is a double interrupt bit (section 9.7 ). bit 2: transmit current-lim it exceeded condition (tcle). set when the 50ma (rms) current limiter is activated, whether the current limiter is enabled or not. this is a double interrupt bit (section 9.7 ). bit 1: transmit open-circuit detect condition (tocd). set when the device detects that the ttip and tring outputs are open-circuited. this is a double interrupt bit (section 9.7 ). bit 0: loss of line-interface transmit-clock condition (lolitc) . set when tdclki has not transitioned for one channel time. this is a double interrupt bit (section 9.7 ).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 212 of 338 register name: tr.imr1 register description: interrupt mask register 1 register address: 17h bit # 7 6 5 4 3 2 1 0 name ilut timer rscos jalt lrcl tcle tocd lolitc default 0 0 0 0 0 0 0 0 bit 7: input level under threshold (ilut) 0 = interrupt masked 1 = interrupt enabled bit 6: timer event (timer) 0 = interrupt masked 1 = interrupt enabled bit 5: receive signaling change-of-state event (rscos) 0 = interrupt masked 1 = interrupt enabled bit 4: jitter attenuator limit trip event (jalt) 0 = interrupt masked 1 = interrupt enabled bit 3: line interface receive carrier-loss condition (lrcl) 0 = interrupt masked 1 = interrupt enabled?generates interrupts on rising and falling edges bit 2: transmit current-lim it exceeded condition (tcle) 0 = interrupt masked 1 = interrupt enabled?generates interrupts on rising and falling edges bit 1: transmit open-circuit detect condition (tocd) 0 = interrupt masked 1 = interrupt enabled?generates interrupts on rising and falling edges bit 0: loss-of-transmit clock condition (lolitc) 0 = interrupt masked 1 = interrupt enabled?generates interrupts on rising and falling edges
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 213 of 338 register name: tr.sr2 register description: status register 2 register address: 18h bit # 7 6 5 4 3 2 1 0 name ryelc rua1c frclc rl osc ryel rua1 frcl rlos default 0 0 0 0 0 0 0 0 bit 7: receive yellow alarm clear event (ryelc) (t1 only). set when the receive yellow alarm condition is no longer detected. bit 6: receive unframed all-ones clear event (rua1c). set when the unframed all 1s condition is no longer detected. bit 5: framer receive carrier-loss clear event (frclc). set when the carrier loss condition at rposi and rnegi is no longer detected. bit 4: receive loss-of-sync clear event (rlosc). set when the framer achieves synchronization; remains set until read. bit 3: receive yellow alarm condition (ryel) (t1 only). set when a yellow alarm is received at rposi and rnegi. bit 2: receive unframed all-ones (t1 bl ue alarm, e1 ais) condition (rua1). set when an unframed all 1s code is received at rposi and rnegi. bit 1: framer receive ca rrier-loss condition (frcl). set when 255 (or 2048 if tr.e1rcr2.0 = 1) e1 mode or 192 t1 mode consecutive 0s have been detected at rposi and rnegi. bit 0: receive loss-of-sync condition (rlos). set when the transceiver is not synchronized to the received data stream.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 214 of 338 register name: tr.imr2 register description: interrupt mask register 2 register address: 19h bit # 7 6 5 4 3 2 1 0 name ryelc rua1c frclc rl osc ryel rua1 frcl rlos default 0 0 0 0 0 0 0 0 bit 7: receive yellow alarm clear event (ryelc) 0 = interrupt masked 1 = interrupt enabled bit 6: receive unframed all-on es condition clear event (rua1c) 0 = interrupt masked 1 = interrupt enabled bit 5: framer receive carri er loss condition clear (frclc) 0 = interrupt masked 1 = interrupt enabled bit 4: receive loss-of-sync clear event (rlosc) 0 = interrupt masked 1 = interrupt enabled bit 3: receive yellow alarm condition (ryel) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only bit 2: receive unframed all-on es (blue alarm) condition (rua1) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only bit 1: framer receive ca rrier loss condition (frcl) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only bit 0: receive loss-of-sync condition (rlos) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 215 of 338 register name: tr.sr3 register description: status register 3 register address: 1ah bit # 7 6 5 4 3 2 1 0 name lspare ldn lup lotc lorc v52lnk rdma rra default 0 0 0 0 0 0 0 0 bit 7: spare code detected condition (lspare) (t1 only). set when the spare code as defined in the tr.rscd1/2 registers is being received. see section 10.20 for details. this is a double interrupt bit. see section 9.7 . bit 6: loop-down code detected condition (ldn) (t1 only). set when the loop down code as defined in the tr.rdncd1/2 register is being received. see section 10.20 for details. this is a double interrupt bit. see section 9.7 . bit 5: loop-up code detected condition (lup) (t1 only). set when the loop-up code as defined in the tr.rupcd1/2 register is being received. see section 10.20 for details. this is a double interrupt bit. see section 9.7 . bit 4: loss-of-transmit clock condition (lotc). set when the tclkt pin has not transitioned for one channel time. forces the lotc pin high if enabled by tr. ccr1.0. this is a double interrupt bit. see section 9.7 . bit 3: loss-of-receive clock condition (lorc). set when the rdclki pin has not transitioned for one channel time. this is a double interrupt bit. see section 9.7 . bit 2: v5.2 link detected condition (v52lnk) (e1 only). set on detection of a v5.2 link identification signal (g.965). this is a double interrupt bit. see section 9.7 . bit 1: receive distant mf alarm condition (rdma) (e1 only). set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. this alarm is not disabled in the ccs signaling mode. this is a double interrupt bit. see section 9.7 . bit 0: receive remote alar m condition (rra) (e1 only). set when a remote alarm is received at rposi and rnegi. this is a double interrupt bit. see section 9.7 .
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 216 of 338 register name: tr.imr3 register description: interrupt mask register 3 register address: 1bh bit # 7 6 5 4 3 2 1 0 name lspare ldn lup lotc lorc v52lnk rdma rra default 0 0 0 0 0 0 0 0 bit 7: spare code detected condition (lspare) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 6: loop-down code-detected condition (ldn) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 5: loop-up code-detected condition (lup) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 4: loss-of-transmit clock condition (lotc) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 3: loss-of-receive clock condition (lorc) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 2: v5.2 link detected condition (v52lnk) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 1: receive distant mf alarm condition (rdma) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 0: receive remote alarm condition (rra) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 217 of 338 register name: tr.sr4 register description: status register 4 register address: 1ch bit # 7 6 5 4 3 2 1 0 name rais-ci rsao rsaz tmf taf rmf rcmf raf default 0 0 0 0 0 0 0 0 bit 7: receive ais-ci event (rais-ci) (t1 only). set when the receiver detects the ais-ci pattern as defined in ansi t1.403. bit 6: receive signaling all-ones event (rsao) (e1 only). set when the contents of time slot 16 contains fewer than three 0s over 16 consecutive frames. this alarm is not disabled in the ccs signaling mode. bit 5: receive signaling all-zeros event (rsaz) (e1 only). set when over a full mf, time slot 16 contains all 0s. bit 4: transmit mult iframe event (tmf) e1 mode: set every 2ms (regardless if crc4 is enabl ed) on transmit multiframe boundaries. used to alert the host that signaling data needs to be updated. t1 mode: set every 1.5ms on d4 mf boundaries or every 3ms on esf mf boundaries. bit 3: transmit align frame event (taf) (e1 only). set every 250s at the beginning of align frames. used to alert the host that the tr.taf and tr.tnaf registers need to be updated. bit 2: receive multiframe event (rmf) e1 mode: set every 2ms (regardless if cas signaling is enabled or not) on receive multiframe boundaries. used to alert the host that signaling data is available. t1 mode: set every 1.5ms on d4 mf boundaries or every 3ms on esf mf boundaries. bit 1: receive crc4 multiframe event (rcmf) (e1 only). set on crc4 multiframe boundaries; continues to set every 2ms on an arbi trary boundary if crc4 is disabled. bit 0: receive align frame event (raf) (e1 only). set every 250s at the beginning of align frames. used to alert the host that si and sa bits are ava ilable in the tr.raf and tr.rnaf registers.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 218 of 338 register name: tr.imr4 register description: interrupt mask register 4 register address: 1dh bit # 7 6 5 4 3 2 1 0 name rais-ci rsao rsaz tmf taf rmf rcmf raf default 0 0 0 0 0 0 0 0 bit 7: receive ais-ci event (rais-ci) 0 = interrupt masked 1 = interrupt enabled bit 6: receive signaling all-ones event (rsao) 0 = interrupt masked 1 = interrupt enabled bit 5: receive signaling all-zeros event (rsaz) 0 = interrupt masked 1 = interrupt enabled bit 4: transmit mult iframe event (tmf) 0 = interrupt masked 1 = interrupt enabled bit 3: transmit align frame event (taf) 0 = interrupt masked 1 = interrupt enabled bit 2: receive multiframe event (rmf) 0 = interrupt masked 1 = interrupt enabled bit 1: receive crc4 multiframe event (rcmf) 0 = interrupt masked 1 = interrupt enabled bit 0: receive align frame event (raf) 0 = interrupt masked 1 = interrupt enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 219 of 338 register name: tr.sr5 register description: status register 5 register address: 1eh bit # 7 6 5 4 3 2 1 0 name ? ? tesf tesem tslip resf resem rslip default 0 0 0 0 0 0 0 0 bit 5: transmit elastic store full event (tesf). set when the transmit elastic store buffer fills and a frame is deleted. bit 4: transmit elastic store empty event (tesem). set when the transmit elastic store buffer empties and a frame is repeated. bit 3: transmit elastic store slip-occurrence event (tslip). set when the transmit elastic store has either repeated or deleted a frame. bit 2: receive elastic store full event (resf). set when the receive elastic store buffer fills and a frame is deleted. bit 1: receive elastic store empty event (resem). set when the receive elastic store buffer empties and a frame is repeated. bit 0: receive elastic store slip-occurrence event (rslip). set when the receive elastic store has either repeated or deleted a frame.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 220 of 338 register name: tr.imr5 register description: interrupt mask register 5 register address: 1fh bit # 7 6 5 4 3 2 1 0 name ? ? tesf tesem tslip resf resem rslip default 0 0 0 0 0 0 0 0 bit 5: transmit elastic store full event (tesf) 0 = interrupt masked 1 = interrupt enabled bit 4: transmit elastic store empty event (tesem) 0 = interrupt masked 1 = interrupt enabled bit 3: transmit elastic store slip-occurrence event (tslip) 0 = interrupt masked 1 = interrupt enabled bit 2: receive elastic store full event (resf) 0 = interrupt masked 1 = interrupt enabled bit 1: receive elastic store empty event (resem) 0 = interrupt masked 1 = interrupt enabled bit 0: receive elastic store slip-occurrence event (rslip) 0 = interrupt masked 1 = interrupt enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 221 of 338 register name: tr.sr6, tr.sr7 register description: hdlc #1 status register 6 hdlc #2 status register 7 register address: 20h, 22h bit # 7 6 5 4 3 2 1 0 name ? tmend rpe rps rhwm rne tlwm tnf default 0 0 0 0 0 0 0 0 bit 6: transmit message-end event (tmend). set when the transmit hdlc controller has finished sending a message. this is a latched bit and is cleared when read. bit 5: receive packet-end event (rpe). set when the hdlc controller detects either the finish of a valid message (i.e., crc check complete) or when the controller has experienced a message fault such as a crc checking error, or an overrun condition, or an abort has been seen. this is a latched bit and is cleared when read. bit 4: receive packet-start event (rps) . set when the hdlc controller detects an opening byte. this is a latched bit and is cleared when read. bit 3: receive fifo above hi gh-watermark condition (rhwm). set when the receive 128-byte fifo fills beyond the high watermark as defined by the receive high-watermark register (tr.rhwmr). bit 2: receive fifo not empty condition (rne). set when the receive 128-byte fifo has at least 1 byte available for a read. bit 1: transmit fifo below low-watermark condition (tlwm). set when the transmit 128-byte fifo empties beyond the low watermark as defined by the transmit low-watermark register (tr.tlwmr). bit 0: transmit fifo not full condition (tnf). set when the transmit 128-byte fifo has at least 1 byte available.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 222 of 338 register name: tr.imr6, tr.imr7 register description: hdlc # 1 interrupt mask register 6 hdlc # 2 interrupt mask register 7 register address: 21h, 23h bit # 7 6 5 4 3 2 1 0 name ? tmend rpe rps rhwm rne tlwm tnf default 0 0 0 0 0 0 0 0 bit 6: transmit message-end event (tmend) 0 = interrupt masked 1 = interrupt enabled bit 5: receive packet-end event (rpe) 0 = interrupt masked 1 = interrupt enabled bit 4: receive packet-start event (rps) 0 = interrupt masked 1 = interrupt enabled bit 3: receive fifo above high-watermark condition (rhwm) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only bit 2: receive fifo not empty condition (rne) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only bit 1: transmit fifo below low-watermark condition (tlwm) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only bit 0: transmit fifo not full condition (tnf) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising edge only
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 223 of 338 register name: tr.info5, tr.info6 register description: hdlc #1 information register hdlc #2 information register register address: 2eh, 2fh bit # 7 6 5 4 3 2 1 0 name ? ? tempty tfull rempty ps2 ps1 ps0 default 0 0 0 0 0 0 0 0 bit 5: transmit fifo empty (tempty). a real-time bit that is set high when the fifo is empty. bit 4: transmit fifo full (tfull). a real-time bit that is set high when the fifo is full. bit 3: receive fifo empty (rempty). a real-time bit that is set high when the receive fifo is empty. bits 0 ? 2: receive packet status (ps0 to ps2) . these are real-time bits indicating the status as of the last read of the receive fifo. ps2 ps1 ps0 packet status 0 0 0 in progress 0 0 1 packet ok: packet ended with correct crc codeword 0 1 0 crc error: a closing flag was detected, preceded by a corrupt crc codeword 0 1 1 abort: packet ended because an abort signal was detected (seven or more 1s in a row). 1 0 0 overrun: hdlc controller terminated reception of packet because receive fifo is full. register name: tr.info4 register description: hdlc event information register #4 register address: 2dh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? h2udr h2obt h1udr h1obt default 0 0 0 0 0 0 0 0 bit 3: hdlc #2 transmit fi fo underrun event (h2udr). set when the transmit fifo empties out without having seen the tmend bit set. an abort is automatically sent. this bit is latched and is cleared when read. bit 2: hdlc #2 opening byte event (h2obt). set when the next byte available in the receive fifo is the first byte of a message. bit 1: hdlc #1 transmit fi fo underrun event (h1udr). set when the transmit fifo empties out without having seen the tmend bit set. an abort is automatically sent. this bit is latched and is cleared when read. bit 0: hdlc #1 opening byte event (h1obt). set when the next byte available in the receive fifo is the first byte of a message.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 224 of 338 register name: tr.sr8 register description: status register 8 register address: 24h bit # 7 6 5 4 3 2 1 0 name ? ? bocc rfdlad rfdlf tfdle rmtch rboc default 0 0 0 0 0 0 0 0 bit 5: boc clear event (bocc). set when 30 fdl bits occur without an abort sequence. bit 4: rfdl abort detect event (rfdlad). set when eight consecutive 1s are received on the fdl. bit 3: rfdl register full event (rfdlf). set when the receive fdl buffer (tr.rfdl) fills to capacity. bit 2: tfdl register empty event (tfdle). set when the transmit fdl buffer (tr.tfdl) empties. bit 1: receive fdl match event (rmtch). set whenever the contents of the tr.rfdl register matches tr.rfdlm1 or tr.rfdlm2. bit 0: receive boc detector change-of-state event (rboc). set whenever the boc detector sees a change of state to a valid boc. the setting of this bit prompts the user to read the tr.rfdl register. register name: tr.imr8 register description: interrupt mask register 8 register address: 25h bit # 7 6 5 4 3 2 1 0 name ? ? bocc rfdlad rfdlf tfdle rmtch rboc default 0 0 0 0 0 0 0 0 bit 5: boc clear event (bocc) 0 = interrupt masked 1 = interrupt enabled bit 4: rfdl abort detect event (rfdlad) 0 = interrupt masked 1 = interrupt enabled bit 3: rfdl register full event (rfdlf) 0 = interrupt masked 1 = interrupt enabled bit 2: tfdl register empty event (tfdle) 0 = interrupt masked 1 = interrupt enabled bit 1: receive fdl match event (rmtch) 0 = interrupt masked 1 = interrupt enabled bit 0: receive boc detector change-of-state event (rboc) 0 = interrupt masked 1 = interrupt enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 225 of 338 register name: tr.sr9 register description: status register 9 register address: 26h bit # 7 6 5 4 3 2 1 0 name ? bbed bbco bec0 bra1 bra0 brlos bsync default 0 0 0 0 0 0 0 0 bit 6: bert bit-error det ected (bed) event (bbed). a latched bit that is set when a bit error is detected. the receive bert must be in synchronization for it to detect bit errors. cleared when read. bit 5: bert bit-counter overflow event (bbco). a latched bit that is set when the 32-bit bert bit counter (bbc) overflows. cleared when read and is not set again until another overflow occurs. bit 4: bert error-counter overflow (beco) event (beco). a latched bit that is set when the 24-bit bert error counter (bec) overflows. cleared when read and is not set again until another overflow occurs. bit 3: bert receive all-ones condition (bra1). a latched bit that is set when 32 consecutive 1s are received. allowed to be cleared once a 0 is received. this is a double interrupt bit (section 9.7 ). bit 2: bert receive all-zeros condition (bra0). a latched bit that is set when 32 consecutive 0s are received. allowed to be cleared once a 1 is received. this is a double interrupt bit (section 9.7 ). bit 1: bert receive loss-of-s ynchronization c ondition (brlos). a latched bit that is set whenever the receive bert begins searching for a pattern. once synchroniza tion is achieved, this bit remains set until read. this is a double interrupt bit (section 9.7 ). bit 0: bert in synchronization condition (bsync). set when the incoming pattern matches for 32 consecutive bit positions. refer to bsync in the tr.info2 register for a real-time version of this bit. this is a double interrupt bit (section 9.7 ).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 226 of 338 register name: tr.imr9 register description: interrupt mask register 9 register address: 27h bit # 7 6 5 4 3 2 1 0 name ? bbed bbco bec0 bra1 bra0 brlos bsync default 0 0 0 0 0 0 0 0 bit 6: bit-error det ected event (bbed) 0 = interrupt masked 1 = interrupt enabled bit 5: bert bit-counter overflow event (bbco) 0 = interrupt masked 1 = interrupt enabled bit 4: bert error-counter overflow event (beco) 0 = interrupt masked 1 = interrupt enabled bit 3: receive all-ones condition (bra1) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 2: receive all-zeros condition (bra0) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 1: receive loss-of-synch ronization condi tion (brlos) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges bit 0: bert in synchronization condition (bsync) 0 = interrupt masked 1 = interrupt enabled?interrupts on rising and falling edges
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 227 of 338 register name: tr.pcpr register description: per-channel pointer register register address: 28h bit # 7 6 5 4 3 2 1 0 name rsaoics rsrcs rfcs b rcs thscs peics tfcs btcs default 0 0 0 0 0 0 0 0 bit 7: receive signaling all-ones insertion channel select (rsaoics) bit 6: receive signaling reinsertion channel select (rsrcs) bit 5: receive fractional channel select (rfcs) bit 4: bert receive channel select (brcs) bit 3: transmit hardware si gnaling channel select (thscs) bit 2: payload error insert channel select (peics) bit 1: transmit fractional channel select (tfcs) bit 0: bert transmit channel select (btcs) see section 10.2 for a general overview of pe r-channel operation. see section 10.10 for more information on per- channel idle code generation. see section 10.6 for more information on per-channel loopback operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 228 of 338 register name: tr.pcdr1 register description: per-channel data register 1 register address: 29h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? default ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 register name: tr.pcdr2 register description: per-channel data register 2 register address: 2ah bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? default ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 register name: tr.pcdr3 register description: per-channel data register 3 register address: 2bh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? default ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 register name: tr.pcdr4 register description: per-channel data register 4 register address: 2ch bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? default ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 see section 10.2 for a general overview of pe r-channel operation. see section 10.10 for more information on per- channel idle code generation. see section 10.6 for more information on per-channel loopback operation.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 229 of 338 register name: tr.info7 register description: information register 7 (real-time, non-latched register) register address: 30h bit # 7 6 5 4 3 2 1 0 name csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa default 0 0 0 0 0 0 0 0 bits 3 ? 7: crc4 sync counter bits (csc0, csc2 to csc4). the crc4 sync counter increments each time the 8ms crc4 multiframe search times out. the counter is cleared when the framer has successfully obtained synchronization at the crc4 level. the counter can al so be cleared by disabling the crc4 mode (tr.e1rcr1.3 = 0). this counter is useful for determining the amount of time the framer has been searching for synchronization at the crc4 level. itu g.706 suggests that if synchronization at the crc4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. t he crc4 sync counter rolls over. csc0 is the lsb of the 6-bit counter. (note: the bit next to lsb is not a ccessible. csc1 is omitted to allow resolution to >400ms using 5 bits.) these are read-only, non-latched, real-time bits. it is not necessary to precede the read of these bits with a write. bit 2: fas sync active (fassa). set while the synchronizer is searching for alignment at the fas level. this is a read-only, non-latched, real-time bit. it is not necessary to precede the read of this bit with a write. bit 1: cas mf sync active (cassa). set while the synchronizer is searching for the cas mf alignment word. this is a read-only, non-latched, real-time bit. it is not necessary to precede the read of this bit with a write. bit 0: crc4 mf sync active (crc4sa). set while the synchronizer is searching for the crc4 mf alignment word. this is a read-only, non-latched, real-time bit. it is not necessary to precede the read of this bit with a write. register name: tr.h1rc, tr.h2rc register description: hdlc #1 receive control hdlc #2 receive control register address: 31h, 32h bit # 7 6 5 4 3 2 1 0 name rhr rhms ? ? ? ? ? rsfd default 0 0 0 0 0 0 0 0 bit 7: receive hdlc reset (rhr). resets the receive hdlc controller and flushes the receive fifo. must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset receive hdlc controller and flush the receive fifo bit 6: receive hdlc mapping select (rhms) 0 = receive hdlc assigned to channels 1 = receive hdlc assigned to fdl (t1 mode), sa bits (e1 mode) bits 1 ? 5: unused, must be set to 0 or proper operation bit 0: receive ss7 fill-in signal unit delete (rsfd) 0 = normal operation; all fisus are stored in the receive fifo and reported to the host. 1 = when a consecutive fisu having the same bsn the previous fisu is detected, it is deleted without host intervention.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 230 of 338 register name: tr.e1rcr1 register description: e1 receive control register 1 register address: 33h bit # 7 6 5 4 3 2 1 0 name rserc rsigm rhdb3 rg802 rcrc4 frc synce resync default 0 0 0 0 0 0 0 0 bit 7: rsero control (rserc) 0 = allow rsero to output data as received under all conditions 1 = force rsero to 1 under loss-of-frame alignment conditions bit 6: receive signaling mode select (rsigm) 0 = cas signaling mode 1 = ccs signaling mode bit 5: receive hdb3 enable (rhdb3) 0 = hdb3 disabled 1 = hdb3 enabled bit 4: receive g.802 enable (rg802). see section 10.10 for details. 0 = do not force rchblk high during bit 1 of time slot 26 1 = force rchblk high during bit 1 of time slot 26 bit 3: receive crc4 enable (rcrc4) 0 = crc4 disabled 1 = crc4 enabled bit 2: frame resync criteria (frc) 0 = resync if fas received in error three consecutive times 1 = resync if fas or bit 2 of non-fas is received in error three consecutive times bit 1: sync enable (synce) 0 = auto resync enabled 1 = auto resync disabled bit 0: resync (resync). when toggled from low to high, a resync is initiated. must be cleared and set again for a subsequent resync. register name: tr.e1rcr2 register description: e1 receive control register 2 register address: 34h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? rcla default 0 0 0 0 0 0 0 0 bit 0: receive carrier-loss (rcl) alternate criteria (rcla). defines the criteria for a receive carrier-loss condition for both the framer and liu. 0 = rcl declared upon 255 consecutive 0s (125s) 1 = rcl declared upon 2048 consecutive 0s (1ms)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 231 of 338 register name: tr.e1tcr1 register description: e1 transmit control register 1 register address: 35h bit # 7 6 5 4 3 2 1 0 name tfpt t16s tua1 tsis tsa1 thdb3 tg802 tcrc4 default 0 0 0 0 0 0 0 0 bit 7: transmit time slot 0 pass-through (tfpt) 0 = fas bits/sa bits/remote alarm sourced internally from the tr.taf and tr.tnaf registers 1 = fas bits/sa bits/remote alarm sourced from tseri bit 6: transmit time slot 16 data select (t16s) 0 = time slot 16 determined by the tr.ssiex registers and the thscs function in the tr.pcpr register 1 = source time slot 16 from tr.ts1 to tr.ts16 registers bit 5: transmit unframed all ones (tua1) 0 = transmit data normally 1 = transmit an unframed all-ones code at tposo and tnego bit 4: transmit international bit select (tsis) 0 = sample si bits at tseri pin 1 = source si bits from tr.taf and tr.tnaf registers (in this mode, tr.e1tcr1.7 must be set to 0) bit 3: transmit signaling all ones (tsa1) 0 = normal operation 1 = force time slot 16 in every frame to all ones bit 2: transmit hdb3 enable (thdb3) 0 = hdb3 disabled 1 = hdb3 enabled bit 1: transmit g.802 enable (tg802). see section 10.10 for details. 0 = do not force tchblk high during bit 1 of time slot 26 1 = force tchblk high during bit 1 of time slot 26 bit 0: transmit crc4 enable (tcrc4) 0 = crc4 disabled 1 = crc4 enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 232 of 338 register name: tr.e1tcr2 register description: e1 transmit control register 2 register address: 36h bit # 7 6 5 4 3 2 1 0 name - - - - - aebe aais ara default 0 0 0 0 0 0 0 0 bit 2: automatic e-bit enable (aebe) 0 = e-bits not automatically set in the transmit direction 1 = e-bits automatically set in the transmit direction bit 1: automatic ais generation (aais) 0 = disabled 1 = enabled bit 0: automatic remote alarm generation (ara) 0 = disabled 1 = enabled register name: tr.bocc register description: boc control register register address: 37h bit # 7 6 5 4 3 2 1 0 name ? ? ? rboce rbr rbf1 rbf0 sboc default 0 0 0 0 0 0 0 0 bit 4: receive boc enable (rboce). enables the receive boc function. the tr.rfdl register reports the received boc code and two information bits when this bit is set. 0 = receive boc function disabled 1 = receive boc function enabled; the tr.rfdl register reports boc messages and information bit 3: receive boc reset (rbr). a 0-to-1 transition resets the boc circuitry. must be cleared and set again for a subsequent reset. bits 1 ? 2: receive boc filter bits (rbf0, rbf1). the boc filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message. rbf1 rbf0 consecutive boc codes for valid sequence identification 0 0 none 0 1 3 1 0 5 1 1 7 bit 0: send boc (sboc). set = 1 to transmit the boc code placed in bits 0 to 5 of the tr.tfdl register.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 233 of 338 register name: tr.rsinfo1, tr.rsinfo2, tr.rsinfo3, tr.rsinfo4 register description: receive signaling change-of-state information register address: 38h, 39h, 3ah, 3bh (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rsinfo1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rsinfo2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rsinfo3 ch30 ch29 ch28 ch27 ch26 ch25 rsinfo4 when a channel?s signaling data changes state, the respective bit in registers tr.rsinfo1?4 is set. an interrupt is generated if the channel was also enabled as an interrupt source by setting the appropriate bit in tr.rscse1?4. the bit remains set until read. register name: tr.rscse1, tr.rscse2, tr.rscse3, tr.rscse4 register description: receive signaling change-of-state interrupt enable register address: 3ch, 3dh, 3eh, 3fh (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rscse1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rscse2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rscse3 ch30 ch29 ch28 ch27 ch26 ch25 rscse4 setting any of the ch1?ch30 bits in the tr.rscse1? tr.rscse4 registers causes an interrupt when that channel?s signaling data changes state.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 234 of 338 register name: tr.sigcr register description: signaling control register register address: 40h bit # 7 6 5 4 3 2 1 0 name grsre ? ? rfe rff rccs tccs frsao default 0 0 0 0 0 0 0 0 bit 7: global receive signaling reinsertion enable (grsre). this bit allows the user to reinsert all signaling channels without programming all channels through the per-channel function. 0 = do not reinsert all signaling 1 = reinsert all signaling bit 4: receive freeze enable (rfe). see section 10.9.2.3 for details. 0 = no freezing of receive signaling data occurs 1 = allow freezing of receive signaling data at rsig (and rsero if receive signaling reinsertion is enabled) bit 3: receive force freeze (rff). freezes receive-side signaling at rsig (and rsero if receive signaling reinsertion is enabled); overrides receive freeze enable (rfe). see section 10.9.2.3 for details. 0 = do not force a freeze event 1 = force a freeze event bit 2: receive time slot cont rol for cas signaling (rccs). controls the order that signaling is placed into the receive signaling registers. this bit should be set = 0 in t1 mode. 0 = signaling data is cas format 1 = signaling data is ccs format bit 1: transmit time slot control for cas signaling (tccs). controls the order that signaling is transmitted from the transmit signaling registers. this bit should be set = 0 in t1 mode. 0 = signaling data is cas format 1 = signaling data is ccs format bit 0: force receive signaling all ones (frsao). in t1 mode, this bit forces all signaling data at the rsig and rsero pin to all ones. this bit has no effect in e1 mode. 0 = normal signaling data at rsig and rsero 1 = force signaling data at rsig and rsero to all ones
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 235 of 338 register name: tr.ercnt register description: error-counter configuration register register address: 41h bit # 7 6 5 4 3 2 1 0 name ? mecu ecus eams vcrfs fsbe moscrf lcvcrf default 0 0 0 0 0 0 0 0 bit 6: manual error-counter update (mecu). when enabled by tr.ercnt.4, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error-counter registers with the latest counts and reset the counters. the user must wait a minimum of 1.5 rclko clock periods before reading the error count registers to allow for proper update. bit 5: error-counter update select (ecus) t1 mode: 0 = update error counters once a second 1 = update error counters every 42ms (333 frames) e1 mode: 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) bit 4: error-accumulation mode select (eams) 0 = tr.ercnt.5 determines accumulation time 1 = tr.ercnt.6 determines accumulation time bit 3: e1 line-code violation c ount register function select (vcrfs) 0 = count bipolar violations (bpvs) 1 = count code violations (cvs) bit 2: pcvcr fs-bit error-report enable (fsbe) 0 = do not report bit errors in fs-bit position; only ft-bit position 1 = report bit errors in fs-bit position as well as ft-bit position bit 1: multiframe out-of-sync count register function select (moscrf) 0 = count errors in the framing bit position 1 = count the number of multiframes out-of-sync bit 0: t1 line-code violation count register function select (lcvcrf) 0 = do not count excessive 0s 1 = count excessive 0s register name: tr.lcvcr1 register description: line-code violation count register 1 register address: 42h bit # 7 6 5 4 3 2 1 0 name lcvc15 lcvc14 lcvc13 lcvc 12 lcvc11 lcvc10 lcvc9 lccv8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: line-code violation counter bits 8 to 15 (l cvc8 to lcvc15). lcv15 is the msb of the 16-bit code violation count.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 236 of 338 register name: tr.lcvcr2 register description: line-code violation count register 2 register address: 43h bit # 7 6 5 4 3 2 1 0 name lcvc7 lcvc6 lcvc5 lcvc 4 lcvc3 lcvc2 lcvc1 lcvc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: line-code violation counter bits 0 to 7 (lcvc0 to lcvc7). lcv0 is the lsb of the 16-bit code violation count. register name: tr.pcvcr1 register description: path code violation count register 1 register address: 44h bit # 7 6 5 4 3 2 1 0 name pcvc15 pcvc14 pcvc13 pcvc 12 pcvc11 pcvc10 pcvc9 pcvc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: path code violation counter bits 8 to 15 (pcvc8 to pcvc15). pcvc15 is the msb of the 16-bit path code violation count. register name: tr.pcvcr2 register description: path code violation count register 2 register address: 45h bit # 7 6 5 4 3 2 1 0 name pcvc7 pcvc6 pcvc5 pcvc 4 pcvc3 pcvc2 pcvc1 pcvc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: path code violation counter bits 0 to 7 (pcvc0 to pcvc7). pcvc0 is the lsb of the 16-bit path code violation count. register name: tr.foscr1 register description: frames out-of-sync count register 1 register address: 46h bit # 7 6 5 4 3 2 1 0 name fos15 fos14 fos13 fos12 fos11 fos10 fos9 fos8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: frames out-of-sync counter bits 8 to 15 (fos8 to fos15). fos15 is the msb of the 16-bit frames out-of-sync count.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 237 of 338 register name: tr.foscr2 register description: frames out-of-sync count register 2 register address: 47h bit # 7 6 5 4 3 2 1 0 name fos7 fos6 fos5 fos4 fos3 fos2 fos1 fos0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: frames out-of-sync counter bits 0 to 7 (fos0 to fos7). fos0 is the lsb of the 16-bit frames out- of-sync count. register name: tr.ebcr1 register description: e-bit count register 1 register address: 48h bit # 7 6 5 4 3 2 1 0 name eb15 eb14 eb13 eb12 eb11 eb10 eb9 eb8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: e-bit counter bits 8 to 15 (eb8 to eb15). eb15 is the msb of the 16-bit e-bit count. register name: tr.ebcr2 register description: e-bit count register 2 register address: 49h bit # 7 6 5 4 3 2 1 0 name eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: e-bit counter bits 0 to 7 (eb0 to eb7). eb0 is the lsb of the 16-bit e-bit count.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 238 of 338 register name: tr.lbcr register description: loopback control register register address: 4ah bit # 7 6 5 4 3 2 1 0 name ? ? ? liuc llb rlb plb flb default 0 0 0 0 0 0 0 0 bit 4: line interface unit mux control (liuc). this is a software version of the liuc pin. when the liuc pin is connected high, the liuc bit has control. when the liuc pin is connected low, the framer and liu are separated and the liuc bit has no effect. 0 = liu internally connected to framer. 1 = liu disconnected from framer. use tpos i/tnegi/tdclki/rposi/rnegi/rdclki pins liuc pin liuc bit condition 0 0 liu and framer separated 0 1 liu and framer separated 1 0 liu and framer connected 1 1 liu and framer separated bit 3: local loopback (llb). when this bit is set to 1, data continues to be transmitted as normal through the transmit side of the transceiver. data being received at rtip and rring are replaced with the data being transmitted. data in this loopback passes through the jitter attenuator. see figure 6-3 for more details. bit 2: remote loopback (rlb) . when this bit is set to 1, data input by the rposi and rnegi pins is transmitted back to the tposo and tnego pins. data continues to pass through the receive-side framer of the transceiver as it would normally. data from the transmit-side formatter is ignored. see figure 6-2 for more details. bit 1: payload loopback (plb). when set to 1, payload loopback is enabled and the following occurs: 1) data is transmitted from the tposo and tnego pins synchronous with rclko instead of tclkt. 2) all the receive side signals continue to operate normally. 3) data at the tseri, tdata, and tsig pins is ignored. t1 mode: normally, this loopback is only enabled when esf framing is being performed but can also be enabled in d4 framing applications. the transceiver loops the 192 bits of payload data (with bpvs corrected) from the receive section back to the transmit section. the fps framing pattern, crc6 calculation, and the fdl bits are not looped back; they are reinserted by the transceiver. e1 mode: the transceiver loops the 248 bits of payload data (with bpvs corrected) from the receive section back to the transmit section. the transmit section modifies the payload as if it was input at tseri. the fas word; si, sa, and e bits; and crc4 are not looped back; they are reinserted by the transceiver. bit 0: framer loopback (flb). when this bit is set to 1, the transceiver loops data from the transmit side back to the receive side. when flb is enabled, the following occurs: 1) t1 mode: an unframed all-ones code is transmitted at tposo and tnego. e1 mode: normal data is transmitted at tposo and tnego. 2) data at rposi and rnegi is ignored. 3) all receive-side signals take on timing synchronous with tclkt instead of rdclki. please note that it is not acceptable to have rclko connected to tclkt during this loopback because this causes an unstable condition.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 239 of 338 register name: tr.pclr1 register description: per-channel loopback enable register 1 register address: 4bh bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 ? 7: per-channel loopback enable for channels 1 to 8 (ch1 to ch8) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel register name: tr.pclr2 register description: per-channel loopback enable register 2 register address: 4ch bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 ? 7: per-channel loopback enable for channels 9 to 16 (ch9 to ch16) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel register name: tr.pclr3 register description: per-channel loopback enable register 3 register address: 4dh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 ? 7: per-channel loopback enable for channels 17 to 24 (ch17 to ch24) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel register name: tr.pclr4 register description: per-channel loopback enable register 4 register address: 4eh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 ? 7: per-channel loopback enable for channels 25 to 32 (ch25 to ch32) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 240 of 338 register name: tr.escr register description: elastic store control register register address: 4fh bit # 7 6 5 4 3 2 1 0 name tesalgn tesr tesmdm t ese resalgn resr resmdm rese default 0 0 0 0 0 0 0 0 bit 7: transmit elastic store align (tesalgn). setting this bit from a 0 to a 1 forces the transmit elastic store?s write/read pointers to a minimum separation of half a frame. no action is taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less than half a frame, the command is executed and the data is disrupted. it should be toggled after tsysclk has been applied and is stable. it must be cleared and set again for a subsequent align. see section 10.12.3 for details. bit 6: transmit elastic store reset (tesr). setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames, maximizing the delay through the transmit elastic store. transmit data is lost during the reset. it should be toggled after tsysclk has been applied and is stable. see section 10.12.3 for details. do not leave this bit set high. bit 5: transmit elastic store minimum-delay mode (tesmdm). see section 10.12.4 for details. 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth bit 4: transmit elastic store enable (tese) 0 = elastic store is bypassed 1 = elastic store is enabled bit 3: receive elastic store align (resalgn). setting this bit from a 0 to a 1 forces the receive elastic store?s write/read pointers to a minimum separation of half a frame. no action is taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less than half a frame, the command is executed and the data is disrupted. it should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 10.12.3 for details. bit 2: receive elastic store reset (resr). setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames, maximizing the delay through the receive elastic store. it should be toggled after rsysclk has been applied and is stable. see section 10.12.3 for details. do not leave this bit set high. bit 1: receive elastic store minimum-delay mode (resmdm). see section 10.12.4 for details. 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth bit 0: receive elastic store enable (rese) 0 = elastic store is bypassed 1 = elastic store is enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 241 of 338 register name: tr.ts1 to tr.ts16 register description: transmit signaling registers (e1 mode, cas format) register address: 50h to 5fh (msb) (lsb) 0 0 0 0 x y x x ts1 ch2-a ch2-b ch2-c ch2-d ch1-a ch1-b ch1-c ch1-d ts2 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d ts3 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d ts4 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d ts5 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d ts6 ch12-a ch12-b ch12-c ch12-d ch11-a ch11-b ch11-c ch11-d ts7 ch14-a ch14-b ch14-c ch14-d ch13-a ch13-b ch13-c ch13-d ts8 ch16-a ch16-b ch16-c ch16-d ch15-a ch15-b ch15-c ch15-d ts9 ch18-a ch18-b ch18-c ch18-d ch17-a ch17-b ch17-c ch17-d ts10 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d ts11 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d ts12 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d ts13 ch26-a ch26-b ch26-c ch26-d ch25-a ch25-b ch25-c ch25-d ts14 ch28-a ch28-b ch28-c ch28-d ch27-a ch27-b ch27-c ch27-d ts15 ch30-a ch30-b ch30-c ch30-d ch29-a ch29-b ch29-c ch29-d ts16 register name: tr.ts1 to tr.ts16 register description: transmit signaling registers (e1 mode, ccs format) register address: 50h to 5fh (msb) (lsb) 1 2 3 4 5 6 7 8 ts1 9 10 11 12 13 14 15 16 ts2 17 18 19 20 21 22 23 24 ts3 25 26 27 28 29 30 31 32 ts4 33 34 35 36 37 38 39 40 ts5 41 42 43 44 45 46 47 48 ts6 49 50 51 52 53 54 55 56 ts7 57 58 59 60 61 62 63 64 ts8 65 66 67 68 69 70 71 72 ts9 73 74 75 76 77 78 79 80 ts10 81 82 83 84 85 86 87 88 ts11 89 90 91 92 93 94 95 96 ts12 97 98 99 100 101 102 103 104 ts13 105 106 107 108 109 110 111 112 ts14 113 114 115 116 117 118 119 120 ts15 121 122 123 124 125 126 127 128 ts16
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 242 of 338 register name: tr.ts1 to tr.ts12 register description: transmit signaling registers (t1 mode, esf format) register address: 50h to 5bh (msb) (lsb) ch2-a ch2-b ch2-c ch2-d ch1 -a ch1-b ch1-c ch1-d ts1 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d ts2 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d ts3 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d ts4 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d ts5 ch12-a ch12-b ch12-c ch12-d ch11-a ch11-b ch11-c ch11-d ts6 ch14-a ch14-b ch14-c ch14-d ch13-a ch13-b ch13-c ch13-d ts7 ch16-a ch16-b ch16-c ch16-d ch15-a ch15-b ch15-c ch15-d ts8 ch18-a ch18-b ch18-c ch18-d ch17-a ch17-b ch17-c ch17-d ts9 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d ts10 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d ts11 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d ts12 register name: tr.ts1 to tr.ts12 register description: transmit signaling registers (t1 mode, d4 format) register address: 50h to 5bh (msb) (lsb) ch2-a ch2-b ch2-a ch2-b ch1-a ch1-b ch1-a ch1-b ts1 ch4-a ch4-b ch4-a ch4-b ch3-a ch3-b ch3-a ch3-b ts2 ch6-a ch6-b ch6-a ch6-b ch5-a ch5-b ch5-a ch5-b ts3 ch8-a ch8-b ch8-a ch8-b ch7-a ch7-b ch7-a ch7-b ts4 ch10-a ch10-b ch10-a ch10-b ch9-a ch9-b ch9-a ch9-b ts5 ch12-a ch12-b ch12-a ch12-b ch11-a ch11-b ch11-a ch11-b ts6 ch14-a ch14-b ch14-a ch14-b ch13-a ch13-b ch13-a ch13-b ts7 ch16-a ch16-b ch16-a ch16-b ch15-a ch15-b ch15-a ch15-b ts8 ch18-a ch18-b ch18-a ch18-b ch17-a ch17-b ch17-a ch17-b ts9 ch20-a ch20-b ch20-a ch20-b ch19-a ch19-b ch19-a ch19-b ts10 ch22-a ch22-b ch22-a ch22-b ch21-a ch21-b ch21-a ch21-b ts11 ch24-a ch24-b ch24-a ch24-b ch23-a ch23-b ch23-a ch23-b ts12 note: in d4 format, tr.ts1? tr.ts12 contain signaling data for two frames. bold type indicates data for second frame.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 243 of 338 register name: tr.rs1 to tr.rs12 register description: receive signaling registers (t1 mode, esf format) register address: 60h to 6bh (msb) (lsb) ch2-a ch2-b ch2-c ch2-d ch1 -a ch1-b ch1-c ch1-d rs1 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d rs2 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d rs3 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d rs4 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d rs5 ch12-a ch12-b ch12-c ch12-d ch11- a ch11-b ch11-c ch11-d rs6 ch14-a ch14-b ch14-c ch14-d ch13-a ch13-b ch13-c ch13-d rs7 ch16-a ch16-b ch16-c ch16-d ch15- a ch15-b ch15-c ch15-d rs8 ch18-a ch18-b ch18-c ch18-d ch17- a ch17-b ch17-c ch17-d rs9 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d rs10 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d rs11 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d rs12 register name: tr.rs1 to tr.rs12 register description: receive signaling registers (t1 mode, d4 format) register address: 60h to 6bh (msb) (lsb) ch2-a ch2-b ch2-a ch2-b ch1-a ch1-b ch1-a ch1-b rs1 ch4-a ch4-b ch4-a ch4-b ch3-a ch3-b ch3-a ch3-b rs2 ch6-a ch6-b ch6-a ch6-b ch5-a ch5-b ch5-a ch5-b rs3 ch8-a ch8-b ch8-a ch8-b ch7-a ch7-b ch7-a ch7-b rs4 ch10-a ch10-b ch10-a ch10-b ch9-a ch9-b ch9-a ch9-b rs5 ch12-a ch12-b ch12-a ch12-b ch11-a ch11-b ch11-a ch11-b rs6 ch14-a ch14-b ch14-a ch14-b ch13-a ch13-b ch13-a ch13-b rs7 ch16-a ch16-b ch16-a ch16-b ch15-a ch15-b ch15-a ch15-b rs8 ch18-a ch18-b ch18-a ch18-b ch17-a ch17-b ch17-a ch17-b rs9 ch20-a ch20-b ch20-a ch20-b ch19-a ch19-b ch19-a ch19-b rs10 ch22-a ch22-b ch22-a ch22-b ch21-a ch21-b ch21-a ch21-b rs11 ch24-a ch24-b ch24-a ch24-b ch23-a ch23-b ch23-a ch23-b rs12 note: in d4 format, tr.ts1? tr.ts12 contain signaling data for two frames. bold type indicates data for second frame.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 244 of 338 register name: tr.rs1 to tr.rs16 register description: receive signaling registers (e1 mode, cas format) register address: 60h to 6fh (msb) (lsb) 0 0 0 0 x y x x rs1 ch2-a ch2-b ch2-c ch2-d ch1-a ch1-b ch1-c ch1-d rs2 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d rs3 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d rs4 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d rs5 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d rs6 ch12-a ch12-b ch12-c ch12-d ch11-a ch11-b ch11-c ch11-d rs7 ch14-a ch14-b ch14-c ch14-d ch13- a ch13-b ch13-c ch13-d rs8 ch16-a ch16-b ch16-c ch16-d ch15- a ch15-b ch15-c ch15-d rs9 ch18-a ch18-b ch18-c ch18-d ch17-a ch17-b ch17-c ch17-d rs10 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d rs11 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d rs12 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d rs13 ch26-a ch26-b ch26-c ch26-d ch25-a ch25-b ch25-c ch25-d rs14 ch28-a ch28-b ch28-c ch28-d ch27-a ch27-b ch27-c ch27-d rs15 ch30-a ch30-b ch30-c ch30-d ch29-a ch29-b ch29-c ch29-d rs16 register name: tr.rs1 to tr.rs16 register description: receive signaling registers (e1 mode, ccs format) register address: 60h to 6fh (msb) (lsb) 1 2 3 4 5 6 7 8 rs1 9 10 11 12 13 14 15 16 rs2 17 18 19 20 21 22 23 24 rs3 25 26 27 28 29 30 31 32 rs4 33 34 35 36 37 38 39 40 rs5 41 42 43 44 45 46 47 48 rs6 49 50 51 52 53 54 55 56 rs7 57 58 59 60 61 62 63 64 rs8 65 66 67 68 69 70 71 72 rs9 73 74 75 76 77 78 79 80 rs10 81 82 83 84 85 86 87 88 rs11 89 90 91 92 93 94 95 96 rs12 97 98 99 100 101 102 103 104 rs13 105 106 107 108 109 110 111 112 rs14 113 114 115 116 117 118 119 120 rs15 121 122 123 124 125 126 127 128 rs16
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 245 of 338 register name: tr.ccr1 register description: common control register 1 register address: 70h bit # 7 6 5 4 3 2 1 0 name mclks crc4r sie odm dicai tcss1 tcss0 rlosf default 0 0 0 0 0 0 0 0 bit 7: mclk source (mclks). selects the source of mclk 0 = mclk is source from the mclk pin 1 = mclk is source from the tsysclk pin bit 6: crc-4 recalculate (crc4r) 0 = transmit crc-4 generation and in sertion operates in normal mode 1 = transmit crc-4 generati on operates according to g.706 intermediate path recalculation method bit 5: signaling integration enable (sie) 0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for three multiframes in order for a change of state to be reported bit 4: output data mode (odm) 0 = pulses at tposo and tnego are one full tclko period wide 1 = pulses at tposo and tnego are one-half tclko period wide bit 3: disable idle code auto increment (dicai). selects/deselects the auto-increment feature for the transmit and receive idle code array address register. see section 10.10 . 0 = addresses in tr.iaar register automatically increment on every read/write operation to the tr.pcicr register 1 = addresses in tr.iaar register do not automatically increment bit 2: transmit clock source select bit 0 (tcss1) tcss1 tcss0 transmit clock source 0 0 the tclkt pin is always the source of transmit clock. 0 1 switch to the clock present at rclko when the signal at the tclkt pin fails to transition after 1 channel time. 1 0 use the scaled signal present at mclk as the transmit clock. the tclkt pin is ignored. 1 1 use the signal present at rclko as the transmit clock. the tclkt pin is ignored. bit 1: transmit clock source select bit 0 (tcss0) bit 0: function of the rlos/lotc output (rlosf) 0 = receive loss of sync (rlos) 1 = loss-of-transmit clock (lotc)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 246 of 338 register name: tr.ccr2 register description: common control register 2 register address: 71h bit # 7 6 5 4 3 2 1 0 name bpcs1 bpcs0 bpen default 0 0 0 0 0 0 0 0 bits 1 ? 2: backplane clock selects (bpcs0, bpcs1) bpcs1 bpcs0 bpclk frequency (mhz) 0 0 16.384 0 1 8.192 1 0 4.096 1 1 2.048 bit 0: backplane clock enable (bpen) 0 = disable bpclk pin (pin held at logic 0) 1 = enable bpclk pin register name: tr.ccr3 register description: common control register 3 register address: 72h bit # 7 6 5 4 3 2 1 0 name tmss intdis - - tdatfmt tgpcken rdatfmt rgpcken default 0 0 0 0 0 0 0 0 bit 7: transmit multiframe sync source (tmss). should be set = 0 only when transmit hardware signaling is enabled. 0 = elastic store is source of multiframe sync 1 = framer or tsync pin is source of multiframe sync bit 6: interrupt disable (intdis). this bit is convenient for disabling interrupts without altering the various interrupt mask register settings. 0 = interrupts are enabled according to the various mask register settings 1 = interrupts are disabled regardless of the mask register settings bit 3: transmit channel-data format (tdatfmt) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in seven out of the 8 bits) bit 2: transmit gapped-clock enable (tgpcken) 0 = tchclk functions normally 1 = enable gapped bit-clock output on tchclk bit 1: receive channel-data format (rdatfmt) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in seven out of the 8 bits) bit 0: receive gapped-clock enable (rgpcken) 0 = rchclk functions normally 1 = enable gapped bit-clock output on rchclk
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 247 of 338 register name: tr.ccr4 register description: common control register 4 register address: 73h bit # 7 6 5 4 3 2 1 0 name rlt3 rlt2 rlt1 rlt0 - - - - default 0 0 0 0 0 0 0 0 bits 4 ? 7: receive level threshold bits (rlt0 to rlt3) rlt3 rlt2 rlt1 rlt0 receive level (db) 0 0 0 0 greater than -2.5 0 0 0 1 -2.5 0 0 1 0 -5.0 0 0 1 1 -7.5 0 1 0 0 -10.0 0 1 0 1 -12.5 0 1 1 0 -15.0 0 1 1 1 -17.5 1 0 0 0 -20.0 1 0 0 1 -22.5 1 0 1 0 -25.0 1 0 1 1 -27.5 1 1 0 0 -30.0 1 1 0 1 -32.5 1 1 1 0 -35.0 1 1 1 1 less than -37.5 register name: tr.tds0sel register description: transmit channel monitor select register address: 74h bit # 7 6 5 4 3 2 1 0 name ? ? ? tcm4 tcm3 tcm2 tcm1 tcm0 default 0 0 0 0 0 0 0 0 bits 0 ? 4: transmit channel monitor bits (tcm0 to tcm4). tcm0 is the lsb of a 5-bit channel select that determines which transmit channel data appear in the tr.tds0m register.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 248 of 338 register name: tr.tds0m register description: transmit ds0 monitor register register address: 75h bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit ds0 channel bits (b1 to b8). transmit channel data that has been selected by the transmit channel monitor select register. b8 is the lsb of the ds0 channel (last bit to be transmitted). register name: tr.rds0sel register description: receive channel monitor select register address: 76h bit # 7 6 5 4 3 2 1 0 name ? ? ? rcm4 rcm3 rcm2 rcm1 rcm0 default 0 0 0 0 0 0 0 0 bits 0 ? 4: receive channel monitor bits (rcm0 to rcm4). rcm0 is the lsb of a 5-bit channel select that determines which receive ds0 channel data appear in the tr.rds0m register. register name: tr.rds0m register description: receive ds0 monitor register register address: 77h bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive ds0 channel bits (b1 to b8). receive channel data that has been selected by the receive channel monitor select register. b8 is the l sb of the ds0 channel (last bit to be received).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 249 of 338 register name: tr.lic1 register description: line interface control 1 register address: 78h bit # 7 6 5 4 3 2 1 0 name l2 l1 l0 egl jas jabds dja tpd default 0 0 0 0 0 0 0 0 bits 5 ? 7: line build-out select (l0 to l2). when using the internal termination, the user needs only to select 000 for 75  operation or 001 for 120  operation below. this selects the proper voltage levels for 75  or 120  operation. using tt0 and tt1 of the tr.licr4 register, the user can then select the proper internal source termination. line build-outs 100 and 101 are for backwards compatibility with older products only. e1 mode l2 l1 l0 application n (1) return loss rt (1) ( ? ) 0 0 0 75  normal 1:2 nm 0 0 0 1 120  normal 1:2 nm 0 1 0 0 75  with high return loss * 1:2 21db 6.2 1 0 1 120  with high return loss * 1:2 21db 11.6 *tt0 and tt1 of lic4 register must be set to 0 in this configuration. t1 mode l2 l1 l0 application n (1) return loss rt (1) ( ? ) 0 0 0 dsx-1 (0ft to 133ft) / 0db csu 1:2 nm 0 0 0 1 dsx-1 (133ft to 266ft) 1:2 nm 0 0 1 0 dsx-1 (266ft to 399ft) 1:2 nm 0 0 1 1 dsx-1 (399ft to 533ft) 1:2 nm 0 1 0 0 dsx-1 (533ft to 655ft) 1:2 nm 0 1 0 1 -7.5db csu 1:2 nm 0 1 1 0 -15db csu 1:2 nm 0 1 1 1 -22.5db csu 1:2 nm 0 bit 4: receive equalizer gain limit (egl). this bit controls the sensitivity of the receive equalizer. t1 mode e1 mode 0 = -36db (long haul) 0 = -12db (short haul) 1 = -15db (limited long haul) 1 = -43db (long haul) bit 3: jitter attenuator select (jas) 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side bit 2: jitter attenuator buffer depth select (jabds) 0 = 128 bits 1 = 32 bits (use for delay-sensitive applications) bit 1: disable jitter attenuator (dja) 0 = jitter attenuator enabled 1 = jitter attenuator disabled bit 0: transmit power-down (tpd) 0 = powers down the transmitter and tri-states the ttip and tring pins 1 = normal transmitter operation
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 250 of 338 register name: tr.tlbc register description: transmit line build-out control register address: 7dh bit # 7 6 5 4 3 2 1 0 name - agce gc5 gc4 gc3 gc2 gc1 gc0 default 0 0 0 0 0 0 0 0 bit 6: automatic gain c ontrol enable (agce). 0 = use transmit agc, tr.tlbc bits 0?5 are ?don?t care? 1 = do not use transmit agc, tr.tlbc bits 0?5 set nominal level bits 0?5: gain control bits (gc0?gc5 ). the gc0 through gc5 bits control the gain setting for the nonautomatic gain mode. use the tables below for setting the recommended va lues. the lb (line build-out) column refers to the value in the l0?l2 bits in tr.lic1 (line interface control 1) register. network mode lb gc5 gc4 gc3 gc2 gc1 gc0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 2 0 1 1 0 1 0 3 1 0 0 0 0 0 4 1 0 0 1 1 1 5 1 0 0 1 1 1 6 0 1 0 0 1 1 t1, impedance match off 7 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 2 0 1 0 1 0 1 3 0 1 1 0 1 0 4 1 0 0 0 1 0 5 1 0 0 0 0 0 6 0 0 1 1 0 0 t1, impedance match on 7 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 1 4 1 0 1 0 1 0 e1, impedance match off 5 1 0 1 0 0 0 0 0 1 1 0 1 0 e1, impedance match on 1 0 1 1 0 1 0
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 251 of 338 register name: tr.lic2 register description: line interface control 2 register address: 79h bit # 7 6 5 4 3 2 1 0 name ets lirst ibpv tua1 jamux ? scld clds default 0 0 0 0 0 0 0 0 bit 7: e1/t1 select (ets) 0 = t1 mode selected 1 = e1 mode selected bit 6: line interface reset (lirst). setting this bit from a 0 to a 1 initiates an internal reset that resets the clock recovery state machine and recenters the jitter attenuator. normally this bit is only toggled on power-up. must be cleared and set again for a subsequent reset. bit 5: insert bpv (ibpv). a 0-to-1 transition on this bit causes a single bpv to be inserted into the transmit data stream. once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive 1s to insert the bpv. this bit must be cleared and set again for a subsequent error to be inserted. bit 4: transmit unframed all ones (tua1). the polarity of this bit is set such that the device transmits an all-ones pattern on power-up or device reset. this bit must be set to a 1 to allow the device to transmit data. the transmission of this data pattern is always timed off of the jaclk. 0 = transmit all ones at ttip and tring 1 = transmit data normally bit 3: jitter attenuator mux (jamux). controls the source for jaclk. 0 = jaclk sourced from mclk (2.048mhz or 1.544mhz at mclk) 1 = jaclk sourced from internal pll (2.048mhz at mclk) bit 1: short-circuit limit di sable (ets = 1) (scld). controls the 50ma (rms) current limiter. 0 = enable 50ma current limiter 1 = disable 50ma current limiter bit 0: custom line driver select (clds). setting this bit to a 1 redefines the operation of the transmit line driver. when this bit is set to a 1 and tr.lic1.5 = tr.lic1.6 = tr.lic1.7 = 0, the device generates a square wave at the ttip and tring outputs instead of a normal waveform. when this bit is set to a 1 and tr.lic1.5 = tr.lic1.6 = tr.lic1.7  0, the device forces ttip and tring outputs to become open-drain drivers instead of their normal push-pull operation. this bit should be set to 0 for normal operation of the device.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 252 of 338 register name: tr.lic3 register description: line interface control 3 register address: 7ah bit # 7 6 5 4 3 2 1 0 name ? tces rces mm1 mm0 rsclke tsclke taoz default 0 0 0 0 0 0 0 0 bit 6: transmit-clock edge select (tces). selects which tdclki edge to sample tposi and tnegi. 0 = sample tposi and tnegi on falling edge of tdclki 1 = sample tposi and tnegi on rising edge of tdclki bit 5: receive-clock edge select (rces). selects which rdclko edge to update rposo and rnego. 0 = update rposo and rnego on rising edge of rdclko 1 = update rposo and rnego on falling edge of rdclko bits 3 ? 4: monitor mode (mm0 to mm1) mm1 mm0 internal linear gain boost (db) 0 0 normal operation (no boost) 0 1 20 1 0 26 1 1 32 bit 2: receive synchronization g.703 clock enable (rsclke) 0 = disable 1.544mhz (t1)/2.048mhz (e1) synchronization receive mode 1 = enable 1.544mhz (t1)/2.048mhz (e1) synchronization receive mode bit 1: transmit synchronization g.703 clock enable (tsclke) 0 = disable 1.544mhz (t1)/2.048mhz (e1) transmit synchronization clock 1 = enable 1.544mhz (t1)/2.048mhz (e1) transmit synchronization clock bit 0: transmit alternate ones and zeros (taoz). transmit a ?101010? pattern (customer disconnect indication signal) at ttip and tring. the transmission of this data pattern is always timed off of tclkt. 0 = disabled 1 = enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 253 of 338 register name: tr.lic4 register description: line interface control 4 register address: 7bh bit # 7 6 5 4 3 2 1 0 name cmie cmii mps1 mps0 tt1 tt0 rt1 rt0 default 0 0 0 0 0 0 0 0 bit 7: cmi enable (cmie) 0 = disable cmi mode 1 = enable cmi mode bit 6: cmi invert (cmii) 0 = cmi normal at ttip and rtip 1 = invert cmi signal at ttip and rtip bits 4 ? 5: mclk prescaler t1 mode: mclk (mhz) mps1 mps0 jamux (tr.lic2.3) 1.544 0 0 0 3.088 0 1 0 6.176 1 0 0 12.352 1 1 0 2.048 0 0 1 4.096 0 1 1 8.192 1 0 1 16.384 1 1 1 e1 mode: mclk (mhz) mps1 mps0 jamux (tr.lic2.3) 2.048 0 0 0 4.096 0 1 0 8.192 1 0 0 16.384 1 1 0 bits 2 ? 3: transmit termination select (tt0, tt1) tt1 tt0 internal transmit-termination configuration 0 0 internal transmit-side termination disabled 0 1 internal transmit -side 75  enabled 1 0 internal transmit -side 100  enabled 1 1 internal transmit -side 120  enabled bits 0 ? 1: receive termination select (rt0, rt1) rt1 rt0 internal receive-termination configuration 0 0 internal receive-side termination disabled 0 1 internal receive-side 75  enabled 1 0 internal receive-side 100  enabled 1 1 internal receive-side 120  enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 254 of 338 register name: tr.iaar register description: idle array address register register address: 7eh bit # 7 6 5 4 3 2 1 0 name gric gtic iaa5 iaa4 iaa3 iaa2 iaa1 iaa0 default 0 0 0 0 0 0 0 0 bit 7: global receive-idle code (gric). setting this bit causes all receive channels to be set to the idle code written to the tr.pcicr register. this bit must be set = 0 for read operations. the value in bits iaa0?iaa5 must be a valid transmit channel (01h to 20h for e1 mode; 01h to 18h for t1 mode). bit 6: global transmit-idle code (gtic). setting this bit causes all transmit channels to be set to the idle code written to the pcicr register. this bit must be set = 0 for read operations. the value in bits iaa0?iaa5 must be a valid transmit channel (01h to 20h for e1 mode; 01h to 18h for t1 mode). gric gtic function 0 0 updates a single transmit or receive channel 0 1 updates all transmit channels 1 0 updates all receive channels 1 1 updates all transmit and receive channels bits 0 ? 5: channel pointer address bits (iaa0 to iaa5). these bits select the channel to be programmed with the idle code defined in the tr.pcicr register. iaa0 is the lsb of the 5-bit channel code. channel 1 is 01h. register name: tr.pcicr register description: per-channel idle code register register address: 7fh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: per-channel idle-code bits (c0 to c7). this register defines the idle code to be programmed in the channel selected by the tr.iaar register. c0 is the lsb of the idle code (this bit is transmitted last). register name: tr.tcice1 register description: transmit-channel idle-code enable register 1 register address: 80h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 1 to 8 code insertion control bits (ch1 to ch8) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle-code array into the transmit data stream
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 255 of 338 register name: tr.tcice2 register description: transmit-channel idle-code enable register 2 register address: 81h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 9 to 16 code insertion control bits (ch9 to ch16) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle code-array into the transmit data stream register name: tr.tcice3 register description: transmit-channel idle-code enable register 3 register address: 82h bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 17 to 24 code insertion control bits (ch17 to ch24) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle code-array into the transmit data stream register name: tr.tcice4 register description: transmit-channel idle-code enable register 4 register address: 83h bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 25 to 32 code insertion control bits (ch25 to ch32) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle-code array into the transmit data stream register name: tr.rcice1 register description: receive-channel idle-code enable register 1 register address: 84h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 1 to 8 code insertion control bits (ch1 to ch8) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 256 of 338 register name: tr.rcice2 register description: receive-channel idle-code enable register 2 register address: 85h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 9 to 16 code insertion control bits (ch9 to ch16) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream register name: tr.rcice3 register description: receive-channel idle-code enable register 3 register address: 86h bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 17 to 24 code insertion control bits (ch17 to ch24) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream register name: tr.rcice4 register description: receive-channel idle-code enable register 4 register address: 87h bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 25 to 32 code insertion control bits (ch25 to ch32) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream register name: tr.rcbr1 register description: receive channel blocking register 1 register address: 88h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 1 to 8 channel blocking control bits (ch1 to ch8) 0 = force the rchblk pin to rema in low during this channel time 1 = force the rchblk pin hi gh during this channel time
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 257 of 338 register name: tr.rcbr2 register description: receive channel blocking register 2 register address: 89h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 9 to 16 channel blocking control bits (ch9 to ch16) 0 = force the rchblk pin to rema in low during this channel time 1 = force the rchblk pin hi gh during this channel time register name: tr.rcbr3 register description: receive channel blocking register 3 register address: 8ah bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 17 to 24 channel blocking control bits (ch17 to ch24) 0 = force the rchblk pin to rema in low during this channel time 1 = force the rchblk pin hi gh during this channel time register name: tr.rcbr4 register description: receive channel blocking register 4 register address: 8bh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive channels 25 to 32 channel blocking control bits (ch25 to ch32) 0 = force the rchblk pin to rema in low during this channel time 1 = force the rchblk pin hi gh during this channel time
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 258 of 338 register name: tr.tcbr1 register description: transmit channel blocking register 1 register address: 8ch bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 1 to 8 channel blocking control bits (ch1 to ch8) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time register name: tr.tcbr2 register description: transmit channel blocking register 2 register address: 8dh bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 9 to 16 channel blocking control bits (ch9 to ch16) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time register name: tr.tcbr3 register description: transmit channel blocking register 3 register address: 8eh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 17 to 24 channel blocking control bits (ch17 to ch24) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time register name: tr.tcbr4 register description: transmit channel blocking register 4 register address: 8fh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit channels 25 to 32 channel blocking control bits (ch25 to ch32) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 259 of 338 register name: tr.h1tc, tr.h2tc register description: hdlc #1 transmit control hdlc #2 transmit control register address: 90h, a0h bit # 7 6 5 4 3 2 1 0 name nofs teoml thr thms tfs teom tzsd tcrcd default 0 0 0 0 0 0 0 0 bit 7: number of flags select (nofs) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages bit 6: transmit end of message and loop (teoml). to loop on a message, this bit should be set to a 1 just before the last data byte of an hdlc packet is written into the transmit fifo. the message repeats until the user clears this bit or a new message is written to the transmit fifo. if the host clears the bit, the looping message completes, then flags are transmitted until a new message is written to the fifo. if the host terminates the loop by writing a new message to the fifo, the loop terminates, one or two flags are transmitted, and the new message starts. if not disabled through tcrcd, the transmitter aut omatically appends a 2-byte crc code to the end of all messages. this is useful for transmitting consecutive ss7 fisus without host intervention. bit 5: transmit hdlc reset (thr). resets the transmit hdlc controller and flushes the transmit fifo. an abort followed by 7eh or ffh flags/idle is transmitted until a new packet is initiated by writing new data into the fifo. must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset transmit hdlc controller and flush the transmit fifo bit 4: transmit hdlc mapping select (thms) 0 = transmit hdlc assigned to channels 1 = transmit hdlc assigned to fdl (t1 mode), sa bits (e1 mode) bit 3: transmit flag/idle select (tfs). this bit selects the intermessage fill character after the closing and before the opening flags (7eh). 0 = 7eh 1 = ffh bit 2: transmit end of message (teom). should be set to a 1 just before the last data byte of an hdlc packet is written into the transmit fifo at hxtf. if not dis abled through tcrcd, the transmitter automatically appends a 2- byte crc code to the end of the message. bit 1: transmit zero-stuffer defeat (tzsd). the zero-stuffer function automatically inserts a 0 in the message field (between the flags) after five consecutive 1s to prevent the emulation of a flag or abort sequence by the data pattern. the receiver automatically removes (destuffs) any 0 after five 1s in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer bit 0: transmit crc defeat (tcrcd). a 2-byte crc code is automatically appended to the outbound message. this bit can be used to disable the crc function. 0 = enable crc generation ( normal operation) 1 = disable crc generation
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 260 of 338 register name: tr.h1fc, tr.h2fc register description: hdlc # 1 fifo control hdlc # 2 fifo control register address: 91h, a1h bit # 7 6 5 4 3 2 1 0 name ? ? tflwm2 tflwm1 tflwm0 rfhwm2 rfhwm1 rfhwm0 default 0 0 0 0 0 0 0 0 bits 3 ? 5: transmit fifo low-watermark select (tflwm0 to tflwm2) tflwm2 tflwm1 tflwm0 transmit fifo watermark (bytes) 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112 bits 0 ? 2: receive fifo high-watermark select (rfhwm0 to rfhwm2) rfhwm2 rfhwm1 rfhwm0 receive fifo watermark (bytes) 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 261 of 338 register name: tr.h1rcs1, tr.h1rcs2, tr.h1rcs3, tr.h1rcs4 tr.h2rcs1, tr.h2rcs2, tr.h2rcs3, tr.h2rcs4 register description: hdlc # 1 receive channel select hdlc # 2 receive channel select register address: 92h, 93h, 94h, 95h a2h, a3h, a4h, a5h bit # 7 6 5 4 3 2 1 0 name rhcs7 rhcs6 rhcs5 rhcs 4 rhcs3 rhcs2 rhcs1 rhcs0 default 0 0 0 0 0 0 0 0 bit 7: receive hdlc channe l select bit 7 (rhcs7). select channel 8, 16, 24, or 32. bit 6: receive hdlc channe l select bit 6 (rhcs6). select channel 7, 15, 23, or 31. bit 5: receive hdlc channe l select bit 5 (rhcs5). select channel 6, 14, 22, or 30. bit 4: receive hdlc channe l select bit 4 (rhcs4). select channel 5, 13, 21, or 29. bit 3: receive hdlc channe l select bit 3 (rhcs3). select channel 4, 12, 20, or 28. bit 2: receive hdlc channe l select bit 2 (rhcs2). select channel 3, 11, 19, or 27. bit 1: receive hdlc channe l select bit 1 (rhcs1). select channel 2, 10, 18, or 26. bit 0: receive hdlc channe l select bit 0 (rhcs0). select channel 1, 9, 17, or 25.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 262 of 338 register name: tr.h1rtsbs, tr.h2rtsbs register description: hdlc # 1 receive time slot bits/sa bits select hdlc # 2 receive time slot bits/sa bits select register address: 96h, a6h bit # 7 6 5 4 3 2 1 0 name rcb8se rcb7se rcb6se rcb5se rcb4se rcb3se rcb2se rcb1se default 0 0 0 0 0 0 0 0 bit 7: receive channel bit 8 suppress enable (rcb8se). msb of the channel. set to 1 to stop this bit from being used. bit 6: receive channel bit 7 suppress enable (rcb7se). set to 1 to stop this bit from being used. bit 5: receive channel bit 6 suppress enable (rcb6se). set to 1 to stop this bit from being used. bit 4: receive channel bit 5 suppress enable/sa4 bit enable (rcb5se). set to 1 to stop this bit from being used. bit 3: receive channel bit 4 suppress enable/sa5 bit enable (rcb4se). set to 1 to stop this bit from being used. bit 2: receive channel bit 3 suppress enable/sa6 bit enable (rcb3se). set to 1 to stop this bit from being used. bit 1: receive channel bit 2 suppress enable/sa7 bit enable (rcb2se). set to 1 to stop this bit from being used. bit 0: receive channel bit 1 suppress enable/sa8 bit enable (rcb1se ). lsb of the channel. set to 1 to stop this bit from being used.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 263 of 338 register name: tr.h1tcs1, tr.h1tcs2, tr.h1tcs3, tr.h1tcs4 tr.h2tcs1, tr.h2tcs2, tr.h2tcs3, tr.h2tcs4 register description: hdlc # 1 transmit channel select hdlc # 2 transmit channel select register address: 97h, 98h, 99h, 9ah a7h, a8h, a9h, aah bit # 7 6 5 4 3 2 1 0 name thcs7 thcs6 thcs5 thcs 4 thcs3 thcs2 thcs1 thcs0 default 0 0 0 0 0 0 0 0 bit 7: transmit hdlc cha nnel select bit 7 (thcs7). select channel 8, 16, 24, or 32. bit 6: transmit hdlc cha nnel select bit 6 (thcs6). select channel 7, 15, 23, or 31. bit 5: transmit hdlc cha nnel select bit 5 (thcs5). select channel 6, 14, 22, or 30. bit 4: transmit hdlc cha nnel select bit 4 (thcs4). select channel 5, 13, 21, or 29. bit 3: transmit hdlc cha nnel select bit 3 (thcs3). select channel 4, 12, 20, or 28. bit 2: transmit hdlc cha nnel select bit 2 (thcs2). select channel 3, 11, 19, or 27. bit 1: transmit hdlc cha nnel select bit 1 (thcs1). select channel 2, 10, 18, or 26. bit 0: transmit hdlc cha nnel select bit 0 (thcs0). select channel 1, 9, 17, or 25.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 264 of 338 register name: tr.h1ttsbs, tr.h2ttsbs register description: hdlc # 1 transmit time slot bits/sa bits select hdlc # 2 transmit time slot bits/sa bits select register address: 9bh, abh bit # 7 6 5 4 3 2 1 0 name tcb8se tcb7se tcb6se tcb5se tcb4se tcb3se tcb2se tcb1se default 0 0 0 0 0 0 0 0 bit 7: transmit channel bit 8 suppress enable (tcb1se). msb of the channel. set to 1 to stop this bit from being used. bit 6: transmit channel bit 7 suppress enable (tcb1se). set to 1 to stop this bit from being used. bit 5: transmit channel bit 6 suppress enable (tcb1se). set to 1 to stop this bit from being used. bit 4: transmit channel bit 5 suppress enable/sa4 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 3: transmit channel bit 4 suppress enable/sa5 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 2: transmit channel bit 3 suppress enable/sa6 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 1: transmit channel bit 2 suppress enable/sa7 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 0: transmit channel bit 1 suppress enable/sa8 bit enable (tcb1se). lsb of the channel. set to 1 to stop this bit from being used. register name: tr.h1rpba, tr.h2rpba register description: hdlc # 1 receive packet bytes available hdlc # 2 receive packet bytes available register address: 9ch, ach bit # 7 6 5 4 3 2 1 0 name ms rpba6 rpba5 rpba4 rpba3 rpba2 rpba1 rpba0 default 0 0 0 0 0 0 0 0 bit 7: message status (ms) 0 = bytes indicated by rpba0 through rpba6 are the end of a message. host must check the info5 or info6 register for details. 1 = bytes indicated by rpba0 through rpba6 are the beginning or continuation of a message. the host does not need to check the info5 or info6 register. bits 0 ? 6: receive fifo packet byt es available count (rpba0 to rpba6). rpba0 is the lsb.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 265 of 338 register name: tr.h1tf, tr.h2tf register description: hdlc # 1 transmit fifo hdlc # 2 transmit fifo register address: 9dh, adh bit # 7 6 5 4 3 2 1 0 name thd7 thd6 thd5 thd4 thd3 thd2 thd1 thd0 default 0 0 0 0 0 0 0 0 bit 7: transmit hdlc data bit 7 (thd7). msb of an hdlc packet data byte. bit 6: transmit hdlc data bit 6 (thd6) bit 5: transmit hdlc data bit 5 (thd5) bit 4: transmit hdlc data bit 4 (thd4) bit 3: transmit hdlc data bit 3 (thd3) bit 2: transmit hdlc data bit 2 (thd2) bit 1: transmit hdlc data bit 1 (thd1) bit 0: transmit hdlc data bit 0 (thd0). lsb of an hdlc packet data byte. register name: tr.h1rf, tr.h2rf register description: hdlc # 1 receive fifo hdlc # 2 receive fifo register address: 9eh, aeh bit # 7 6 5 4 3 2 1 0 name rhd7 rhd6 rhd5 rhd4 rhd3 rhd2 rhd1 rhd0 default 0 0 0 0 0 0 0 0 bit 7: receive hdlc data bit 7 (rhd7). msb of an hdlc packet data byte. bit 6: receive hdlc data bit 6 (rhd6) bit 5: receive hdlc data bit 5 (rhd5) bit 4: receive hdlc data bit 4 (rhd4) bit 3: receive hdlc data bit 3 (rhd3) bit 2: receive hdlc data bit 2 (rhd2) bit 1: receive hdlc data bit 1 (rhd1) bit 0: receive hdlc data bit 0 (rhd0). lsb of an hdlc packet data byte.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 266 of 338 register name: tr.h1tfba, tr.h2tfba register description: hdlc # 1 transmit fifo buffer available hdlc # 2 transmit fifo buffer available register address: 9fh, afh bit # 7 6 5 4 3 2 1 0 name tfba7 tfba6 tfba5 tfba4 tfba3 tfba2 tfba1 tfba0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit fifo bytes available (tfbao to tfba7). tfba0 is the lsb. register name: tr.ibcc register description: in-band code control register register address: b6h bit # 7 6 5 4 3 2 1 0 name tc1 tc0 rup2 rup1 rup0 rdn2 rdn1 rdn0 default 0 0 0 0 0 0 0 0 bits 6 ? 7: transmit code length definition bits (tc0 to tc1) tc1 tc0 length selected (bits) 0 0 5 0 1 6/3 1 0 7 1 1 16/8/4/2/1 bits 3 ? 5: receive up-code length definition bits (rup0 to rup2) rup2 rup1 rup0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16 bits 0 ? 2: receive down-code le ngth definition bits (rdn0 to rdn2) rdn2 rdn1 rdn0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 267 of 338 register name: tr.tcd1 register description: transmit code-definition register 1 register address: b7h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bit 7: transmit code-definition bit 7 (c7). first bit of the repeating pattern. bits 3 ? 6: transmit code-definition bits 3?6 (c3?c6) bit 2: transmit code-definition bit 2 (c2). a don?t care if a 5-bit length is selected. bit 1: transmit code-definition bit 1 (c1). a don?t care if a 5-bit or 6-bit length is selected. bit 0: transmit code-definition bit 0 (c0). a don?t care if a 5-, 6-, or 7-bit length is selected. register name: tr.tcd2 register description: transmit code definition register 2 register address: b8h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 least significant byte of 16 bit code. bits 0 ? 7: transmit code-definition bits 0?7 (c0?c7). a don?t care if a 5-, 6-, or 7-bit length is selected.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 268 of 338 register name: tr.rupcd1 register description: receive up-code definition register 1 register address: b9h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detector?s integration period. bit 7: receive up-code definition bit 7 (c7). first bit of the repeating pattern. bit 6: receive up-code definition bit 6 (c6). a don?t care if a 1-bit length is selected. bit 5: receive up-code definition bit 5 (c5). a don?t care if a 1-bit or 2-bit length is selected. bit 4: receive up-code definition bit 4 (c4). a don?t care if a 1-bit to 3-bit length is selected. bit 3: receive up-code definition bit 3 (c3). a don?t care if a 1-bit to 4-bit length is selected. bit 2: receive up-code definition bit 2 (c2). a don?t care if a 1-bit to 5-bit length is selected. bit 1: receive up-code definition bit 1 (c1). a don?t care if a 1-bit to 6-bit length is selected. bit 0: receive up-code definition bit 0 (c0). a don?t care if a 1-bit to 7-bit length is selected. register name: tr.rupcd2 register description: receive up-code definition register 2 register address: bah bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive up-code definition bits 0?7 (c0?c7). a don?t care if a 1-bit to 7-bit length is selected.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 269 of 338 register name: tr.rdncd1 register description: receive down-code definition register 1 register address: bbh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detector?s integration period. bit 7: receive down-code definition bit 7 (c7). first bit of the repeating pattern. bit 6: receive down-code definition bit 6 (c6). a don?t care if a 1-bit length is selected. bit 5: receive down-code definition bit 5 (c5). a don?t care if a 1-bit or 2-bit length is selected. bit 4: receive down-code definition bit 4 (c4). a don?t care if a 1-bit to 3-bit length is selected. bit 3: receive down-code definition bit 3 (c3). a don?t care if a 1-bit to 4-bit length is selected. bit 2: receive down-code definition bit 2 (c2). a don?t care if a 1-bit to 5-bit length is selected. bit 1: receive down-code definition bit 1 (c1). a don?t care if a 1-bit to 6-bit length is selected. bit 0: receive down-code definition bit 0 (c0). a don?t care if a 1-bit to 7-bit length is selected. register name: tr.rdncd2 register description: receive down-code definition register 2 register address: bch bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive down-code definition bits 0?7 (c0?c7). a don?t care if a 1-bit to 7-bit length is selected.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 270 of 338 register name: tr.rscc register description: in-band receive spare control register register address: bdh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? rsc2 rsc1 rsc0 default 0 0 0 0 0 0 0 0 bits 3 ? 7: unused, must be set to 0 for proper operation bits 0 ? 2: receive spare code length definition bits (rsc0 to rsc2) rsc2 rsc1 rsc0 lengt h selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 271 of 338 register name: tr.rscd1 register description: receive spare-code definition register 1 register address: beh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detector?s integration period. bit 7: receive spare-code definition bit 7 (c7). first bit of the repeating pattern. bit 6: receive spare-code definition bit 6 (c6). a don?t care if a 1-bit length is selected. bit 5: receive spare-code definition bit 5 (c5). a don?t care if a 1-bit or 2-bit length is selected. bit 4: receive spare-code definition bit 4 (c4). a don?t care if a 1-bit to 3-bit length is selected. bit 3: receive spare-code definition bit 3 (c3). a don?t care if a 1-bit to 4-bit length is selected. bit 2: receive spare-code definition bit 2 (c2). a don?t care if a 1-bit to 5-bit length is selected. bit 1: receive spare-code definition bit 1 (c1). a don?t care if a 1-bit to 6-bit length is selected. bit 0: receive spare-code definition bit 0 (c0). a don?t care if a 1-bit to 7-bit length is selected. register name: tr.rscd2 register description: receive spare code definition register 2 register address: bfh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive spare-code definition bits 0?7 (c0?c7). a don?t care if a 1-bit to 7-bit length is selected.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 272 of 338 register name: tr.rfdl (tr.bocc.4 = 1) register description: receive fdl register register address: c0h bit # 7 6 5 4 3 2 1 0 name ? ? rboc5 rboc4 rb oc3 rboc2 rboc1 rboc0 default 0 0 0 0 0 0 0 0 rfdl register bit definitions when tr.bocc.4 = 1: bit 5: boc bit 5 (rboc5) bit 4: boc bit 4 (rboc4) bit 3: boc bit 3 (rboc3) bit 2: boc bit 2 (rboc2) bit 1: boc bit 1 (rboc1) bit 0: boc bit 0 (rboc0) register name: tr.rfdl (tr.bocc.4 = 0) register description: receive fdl register register address: c0h bit # 7 6 5 4 3 2 1 0 name rfdl7 rfdl6 rfdl5 rfd l4 rfdl3 rfdl2 rfdl1 rfdl0 default 0 0 0 0 0 0 0 0 the receive fdl register (tr.rfdl) reports the incoming fdl or the incoming fs bits. the lsb is received first. bit 7: receive fdl bit 7 (rfdl7). msb of the received fdl code. bit 6: receive fdl bit 6 (rfdl6) bit 5: receive fdl bit 5 (rfdl5) bit 4: receive fdl bit 4 (rfdl4) bit 3: receive fdl bit 3 (rfdl3) bit 2: receive fdl bit 2 (rfdl2) bit 1: receive fdl bit 1 (rfdl1) bit 0: receive fdl bit 0 (rfdl0). lsb of the received fdl code.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 273 of 338 register name: tr.tfdl register description: transmit fdl register register address: c1h bit # 7 6 5 4 3 2 1 0 name tfdl7 tfdl6 tfdl5 tfdl4 tfdl3 tfdl2 tfdl1 tfdl0 default 0 0 0 0 0 0 0 0 note: also used to insert fs framing pattern in d4 framing mode. the transmit fdl register (tr.tfdl) contains the fdl information that is to be inserted on a byte basis into the outgoing t1 data stream. the lsb is transmitted first. bit 7: transmit fdl bit 7 (tfdl7). msb of the transmit fdl code. bit 6: transmit fdl bit 6 (tfdl6) bit 5: transmit fdl bit 5 (tfdl5) bit 4: transmit fdl bit 4 (tfdl4) bit 3: transmit fdl bit 3 (tfdl3) bit 2: transmit fdl bit 2 (tfdl2) bit 1: transmit fdl bit 1 (tfdl1) bit 0: transmit fdl bit 0 (tfdl0). lsb of the transmit fdl code. register name: tr.rfdlm1, tr.rfdlm2 register description: receive fdl match register 1 receive fdl match register 2 register address: c2h, c3h bit # 7 6 5 4 3 2 1 0 name rfdlm7 rfdlm6 rfdlm5 rfdlm4 rfdlm3 rfdlm2 rfdlm1 rfdlm0 default 0 0 0 0 0 0 0 0 bit 7: receive fdl match bit 7 (rfdlm7). msb of the fdl match code. bit 6: receive fdl match bit 6 (rfdlm6) bit 5: receive fdl match bit 5 (rfdlm5) bit 4: receive fdl match bit 4 (rfdlm4) bit 3: receive fdl match bit 3 (rfdlm3) bit 2: receive fdl match bit 2 (rfdlm2) bit 1: receive fdl match bit 1 (rfdlm1) bit 0: receive fdl match bit 0 (rfdlm0). lsb of the fdl match code.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 274 of 338 register name: tr.raf register description: receive align frame register register address: c6h bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 default 0 0 0 0 0 0 0 0 bit 7: international bit (si) bit 6: frame alignment signal bit (0) bit 5: frame alignment signal bit (0) bit 4: frame alignment signal bit (1) bit 3: frame alignment signal bit (1) bit 2: frame alignment signal bit (0) bit 1: frame alignment signal bit (1) bit 0: frame alignment signal bit (1) register name: tr.rnaf register description: receive nonalign frame register register address: c7h bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 default 0 0 0 0 0 0 0 0 bit 7: international bit (si) bit 6: frame nonalignment signal bit (1) bit 5: remote alarm (a) bit 4: additional bit 4 (sa4) bit 3: additional bit 5 (sa5) bit 2: additional bit 6 (sa6) bit 1: additional bit 7 (sa7) bit 0: additional bit 8 (sa8)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 275 of 338 register name: tr.rsiaf register description: received si bits of the align frame register address: c8h bit # 7 6 5 4 3 2 1 0 name sif0 sif2 sif4 sif6 sif8 sif10 sif12 sif14 default 0 0 0 0 0 0 0 0 bit 7: si bit of frame 0 (sif0) bit 6: si bit of frame 2 (sif2) bit 5: si bit of frame 4 (sif4) bit 4: si bit of frame 6 (sif6) bit 3: si bit of frame 8 (sif8) bit 2: si bit of frame 10 (sif10) bit 1: si bit of frame 12 (sif12) bit 0: si bit of frame 14 (sif14) register name: tr.rsinaf register description: received si bits of the nonalign frame register address: c9h bit # 7 6 5 4 3 2 1 0 name sif1 sif3 sif5 sif7 sif9 sif11 sif13 sif15 default 0 0 0 0 0 0 0 0 bit 7: si bit of frame 1 (sif1) bit 6: si bit of frame 3 (sif3) bit 5: si bit of frame 5 (sif5) bit 4: si bit of frame 7 (sif7) bit 3: si bit of frame 9 (sif9) bit 2: si bit of frame 11 (sif11) bit 1: si bit of frame 13 (sif13) bit 0: si bit of frame 15 (sif15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 276 of 338 register name: tr.rra register description: received remote alarm register address: cah bit # 7 6 5 4 3 2 1 0 name rraf1 rraf3 rraf5 rraf7 rraf9 rraf11 rraf13 rraf15 default 0 0 0 0 0 0 0 0 bit 7: remote alarm bit of frame 1 (rraf1) bit 6: remote alarm bit of frame 3 (rraf3) bit 5: remote alarm bit of frame 5 (rraf5) bit 4: remote alarm bit of frame 7 (rraf7) bit 3: remote alarm bit of frame 9 (rraf9) bit 2: remote alarm bit of frame 11 (rraf11) bit 1: remote alarm bit of frame 13 (rraf13) bit 0: remote alarm bit of frame 15 (rraf15) register name: tr.rsa4 register description: received sa4 bits register address: cbh bit # 7 6 5 4 3 2 1 0 name rsa4f1 rsa4f3 rsa4f5 rsa4f 7 rsa4f9 rsa4f11 rsa4f13 rsa4f15 default 0 0 0 0 0 0 0 0 bit 7: sa4 bit of frame 1 (rsa4f1) bit 6: sa4 bit of frame 3 (rsa4f3) bit 5: sa4 bit of frame 5(rsa4f5) bit 4: sa4 bit of frame 7 (rsa4f7) bit 3: sa4 bit of frame 9 (rsa4f9) bit 2: sa4 bit of frame 11 (rsa4f11) bit 1: sa4 bit of frame 13 (rsa4f13) bit 0: sa4 bit of frame 15 (rsa4f15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 277 of 338 register name: tr.rsa5 register description: received sa5 bits register address: cch bit # 7 6 5 4 3 2 1 0 name rsa5f1 rsa5f3 rsa5f5 rsa5f 7 rsa5f9 rsa5f11 rsa5f13 rsa5f15 default 0 0 0 0 0 0 0 0 bit 7: sa5 bit of frame 1 (rsa5f1) bit 6: sa5 bit of frame 3 (rsa5f3) bit 5: sa5 bit of frame 5 (rsa5f5) bit 4: sa5 bit of frame 7 (rsa5f7) bit 3: sa5 bit of frame 9 (rsa5f9) bit 2: sa5 bit of frame 11 (rsa5f11) bit 1: sa5 bit of frame 13 (rsa5f13) bit 0: sa5 bit of frame 15 (rsa5f15) register name: tr.rsa6 register description: received sa6 bits register address: cdh bit # 7 6 5 4 3 2 1 0 name rsa6f1 rsa6f3 rsa6f5 rsa6f7 rsa6f9 rsa6f11 rsa6f13 rsa6f15 default 0 0 0 0 0 0 0 0 bit 7: sa6 bit of frame 3(rsa6f3) bit 6: sa6 bit of frame 4 (rsa6f4) bit 5: sa6 bit of frame 5 (rsa6f5) bit 4: sa6 bit of frame 7 (rsa6f7) bit 3: sa6 bit of frame 9 (rsa6f9) bit 2: sa6 bit of frame 11 (rsa6f11) bit 1: sa6 bit of frame 13 (rsa6f13) bit 0: sa6 bit of frame 15 (rsa6f15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 278 of 338 register name: tr.rsa7 register description: received sa7 bits register address: ceh bit # 7 6 5 4 3 2 1 0 name rsa7f1 rsa7f3 rsa7f5 rsa7f7 rsa7f9 rsa7f11 rsa7f13 rsa7f15 default 0 0 0 0 0 0 0 0 bit 7: sa7 bit of frame 1(rsa4f1) bit 6: sa7 bit of frame 3 (rsa7f3) bit 5: sa7 bit of frame 5 (rsa7f5) bit 4: sa7 bit of frame 7 (rsa7f7) bit 3: sa7 bit of frame 9 (rsa7f9) bit 2: sa7 bit of frame 11 (rsa7f11) bit 1: sa7 bit of frame 13 (rsa7f13) bit 0: sa7 bit of frame 15 (rsa7f15) register name: tr.rsa8 register description: received sa8 bits register address: cfh bit # 7 6 5 4 3 2 1 0 name rsa8f1 rsa8f3 rsa8f5 rsa8f 7 rsa8f9 rsa8f11 rsa8f13 rsa8f15 default 0 0 0 0 0 0 0 0 bit 7: sa8 bit of frame 1 (rsa8f1) bit 6: sa8 bit of frame 3 (rsa8f3) bit 5: sa8 bit of frame 5 (rsa8f5) bit 4: sa8 bit of frame 7 (rsa8f7) bit 3: sa8 bit of frame 9 (rsa8f9) bit 2: sa8 bit of frame 11 (rsa8f11) bit 1: sa8 bit of frame 13 (rsa8f13) bit 0: sa8 bit of frame 15 (rsa8f15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 279 of 338 register name: tr.taf register description: transmit align frame register register address: d0h bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 default 0 0 0 1 1 0 1 1 bit 7: international bit (si) bit 6: frame alignment signal bit (0) bit 5: frame alignment signal bit (0) bit 4: frame alignment signal bit (1) bit 3: frame alignment signal bit (1) bit 2: frame alignment signal bit (0) bit 1: frame alignment signal bit (1) bit 0: frame alignment signal bit (1) register name: tr.tnaf register description: transmit nonalign frame register register address: d1h bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 default 0 1 0 0 0 0 0 0 bit 7: international bit (si) bit 6: frame nonalignment signal bit (1) bit 5: remote alarm [used to transmit the alarm (a)] bit 4: additional bit 4 (sa4) bit 3: additional bit 5 (sa5) bit 2: additional bit 6 (sa6) bit 1: additional bit 7 (sa7) bit 0: additional bit 8 (sa8)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 280 of 338 register name: tr.tsiaf register description: transmit si bits of the align frame register address: d2h bit # 7 6 5 4 3 2 1 0 name tsif0 tsif2 tsif4 tsif6 tsif8 tsif10 tsif12 tsif14 default 0 0 0 0 0 0 0 0 bit 7: si bit of frame 0 (tsif0) bit 6: si bit of frame 2 (tsif2) bit 5: si bit of frame 4 (tsif4) bit 4: si bit of frame 6 (tsif6) bit 3: si bit of frame 8 (tsif8) bit 2: si bit of frame 10 (tsif10) bit 1: si bit of frame 12 (tsif12) bit 0: si bit of frame 14 (tsif14) register name: tr.tsinaf register description: transmit si bits of the nonalign frame register address: d3h bit # 7 6 5 4 3 2 1 0 name tsif1 tsif3 tsif5 tsif7 tsif9 tsif11 tsif13 tsif15 default 0 0 0 0 0 0 0 0 bit 7: si bit of frame 1 (tsif1) bit 6: si bit of frame 3 (tsif3) bit 5: si bit of frame 5 (tsif5) bit 4: si bit of frame 7 (tsif7) bit 3: si bit of frame 9 (tsif9) bit 2: si bit of frame 11 (tsif11) bit 1: si bit of frame 13 (tsif13) bit 0: si bit of frame 15 (tsif15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 281 of 338 register name: tr.tra register description: transmit remote alarm register address: d4h bit # 7 6 5 4 3 2 1 0 name traf1 traf3 traf5 traf7 traf9 traf11 traf13 traf15 default 0 0 0 0 0 0 0 0 bit 7: remote alarm bit of frame 1 (traf1) bit 6: remote alarm bit of frame 3 (traf3) bit 5: remote alarm bit of frame 5 (traf5) bit 4: remote alarm bit of frame 7 (traf7) bit 3: remote alarm bit of frame 9 (traf9) bit 2: remote alarm bit of frame 11 (traf11) bit 1: remote alarm bit of frame 13 (traf13) bit 0: remote alarm bit of frame 15 (traf15) register name: tr.tsa4 register description: transmit sa4 bits register address: d5h bit # 7 6 5 4 3 2 1 0 name tsa4f1 tsa4f3 tsa4f5 tsa4f7 tsa4f9 tsa4f11 tsa4f13 tsa4f15 default 0 0 0 0 0 0 0 0 bit 7: sa4 bit of frame 1 (tsa4f1) bit 6: sa4 bit of frame 3 (tsa4f3) bit 5: sa4 bit of frame 5 (tsa4f5) bit 4: sa4 bit of frame 7 (tsa4f7) bit 3: sa4 bit of frame 9 (tsa4f9) bit 2: sa4 bit of frame 11 (tsa4f11) bit 1: sa4 bit of frame 13 (tsa4f13) bit 0: sa4 bit of frame 15 (tsa4f15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 282 of 338 register name: tr.tsa5 register description: transmitted sa5 bits register address: d6h bit # 7 6 5 4 3 2 1 0 name tsa5f1 tsa5f3 tsa5f5 tsa5f7 tsa5f9 tsa5f11 tsa5f13 tsa5f15 default 0 0 0 0 0 0 0 0 bit 7: sa5 bit of frame 1 (tsa5f1) bit 6: sa5 bit of frame 3 (tsa5f3) bit 5: sa5 bit of frame 5 (tsa5f5) bit 4: sa5 bit of frame 7 (tsa5f7) bit 3: sa5 bit of frame 9 (tsa5f9) bit 2: sa5 bit of frame 11 (tsa5f11) bit 1: sa5 bit of frame 13 (tsa5f13) bit 0: sa5 bit of frame 15 (tsa5f15) register name: tr.tsa6 register description: transmit sa6 bits register address: d7h bit # 7 6 5 4 3 2 1 0 name tsa6f1 tsa6f3 tsa6f5 tsa6f7 tsa6f9 tsa6f11 tsa6f13 tsa6f15 default 0 0 0 0 0 0 0 0 bit 7: sa6 bit of frame 1 (tsa6f1) bit 6: sa6 bit of frame 3 (tsa6f3) bit 5: sa6 bit of frame 5 (tsa6f5) bit 4: sa6 bit of frame 7 (tsa6f7) bit 3: sa6 bit of frame 9 (tsa6f9) bit 2: sa6 bit of frame 11 (tsa6f11) bit 1: sa6 bit of frame 13 (tsa6f13) bit 0: sa6 bit of frame 15 (tsa6f15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 283 of 338 register name: tr.tsa7 register description: transmit sa7 bits register address: d8h bit # 7 6 5 4 3 2 1 0 name tsa7f1 tsa7f3 tsa7f5 tsa7f7 tsa7f9 tsa7f11 tsa7f13 tsa7f15 default 0 0 0 0 0 0 0 0 bit 7: sa7 bit of frame 1 (tsa4f1) bit 6: sa7 bit of frame 3 (tsa7f3) bit 5: sa7 bit of frame 5 (tsa7f5) bit 4: sa7 bit of frame 7 (tsa7f7) bit 3: sa7 bit of frame 9 (tsa7f9) bit 2: sa7 bit of frame 11 (tsa7f11) bit 1: sa7 bit of frame 13 (tsa7f13) bit 0: sa7 bit of frame 15 (tsa7f15) register name: tr.tsa8 register description: transmit sa8 bits register address: d9h bit # 7 6 5 4 3 2 1 0 name tsa8f1 tsa8f3 tsa8f5 tsa8f7 tsa8f9 tsa8f11 tsa8f13 tsa8f15 default 0 0 0 0 0 0 0 0 bit 7: sa8 bit of frame 1 (tsa8f1) bit 6: sa8 bit of frame 3 (tsa8f3) bit 5: sa8 bit of frame 5 (tsa8f5) bit 4: sa8 bit of frame 7 (tsa8f7) bit 3: sa8 bit of frame 9 (tsa8f9) bit 2: sa8 bit of frame 11 (tsa8f11) bit 1: sa8 bit of frame 13 (tsa8f13) bit 0: sa8 bit of frame 15 (tsa8f15)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 284 of 338 register name: tr.tsacr register description: transmit sa bit control register register address: dah bit # 7 6 5 4 3 2 1 0 name siaf sinaf ra sa4 sa5 sa6 sa7 sa8 default 0 0 0 0 0 0 0 0 bit 7: international bit in ali gn frame insertion control bit (siaf) 0 = do not insert data from the tr.tsiaf register into the transmit data stream 1 = insert data from the tr.tsiaf register into the transmit data stream bit 6: international bit in nonali gn frame insertion control bit (sinaf) 0 = do not insert data from the tr.tsinaf register into the transmit data stream 1 = insert data from the tr.tsinaf register into the transmit data stream bit 5: remote alarm insertion control bit (ra) 0 = do not insert data from the tr.tra register into the transmit data stream 1 = insert data from the tr.tra register into the transmit data stream bit 4: additional bit 4 insertion control bit (sa4) 0 = do not insert data from the tr.tsa4 register into the transmit data stream 1 = insert data from the tr.tsa4 register into the transmit data stream bit 3: additional bit 5 insertion control bit (sa5) 0 = do not insert data from the tr.tsa5 register into the transmit data stream 1 = insert data from the tr.tsa5 register into the transmit data stream bit 2: additional bit 6 insertion control bit (sa6) 0 = do not insert data from the tr.tsa6 register into the transmit data stream 1 = insert data from the tr.tsa6 register into the transmit data stream bit 1: additional bit 7 insertion control bit (sa7) 0 = do not insert data from the tr.tsa7 register into the transmit data stream 1 = insert data from the tr.tsa7 register into the transmit data stream bit 0: additional bit 8 insertion control bit (sa8) 0 = do not insert data from the tr.tsa8 register into the transmit data stream 1 = insert data from the tr.tsa8 register into the transmit data stream register name: tr.bawc register description: bert alternating word-count rate register address: dbh bit # 7 6 5 4 3 2 1 0 name acnt7 acnt6 acnt5 acnt 4 acnt3 acnt2 acnt1 acnt0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: alternating word-count rate bits 0 to 7 (acnt0 to acnt7). acnt0 is the lsb of the 8-bit alternating word-count rate counter.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 285 of 338 register name: tr.brp1 register description: bert repetitive pattern set register 1 register address: dch bit # 7 6 5 4 3 2 1 0 name rpat7 rpat6 rpat5 rpat 4 rpat3 rpat2 rpat1 rpat0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert repetitive pattern set bits 0 to 7 (rpat0 to rpat7) rpat0 is the lsb of the 32-bit repetitive pattern set. register name: tr.brp2 register description: bert repetitive pattern set register 2 register address: ddh bit # 7 6 5 4 3 2 1 0 name rpat15 rpat14 rpat13 rpat 12 rpat11 rpat10 rpat9 rpat8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert repetitive pattern set bits 8 to 15 (rpat8 to rpat15) register name: tr.brp3 register description: bert repetitive pattern set register 3 register address: deh bit # 7 6 5 4 3 2 1 0 name rpat23 rpat22 rpat21 rpat 20 rpat19 rpat18 rpat17 rpat16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert repetitive pattern set bits 16 to 23 (rpat16 to rpat23) register name: tr.brp4 register description: bert repetitive pattern set register 4 register address: dfh bit # 7 6 5 4 3 2 1 0 name rpat31 rpat30 rpat29 rpat 28 rpat27 rpat26 rpat25 rpat24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert repetitive pattern set bits 24 to 31 (rpat24 to rpat31). rpat31 is the lsb of the 32-bit repetitive pattern set.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 286 of 338 register name: tr.bc1 register description: bert control register 1 register address: e0h bit # 7 6 5 4 3 2 1 0 name tc tinv rinv ps2 ps1 ps0 lc resync default 0 0 0 0 0 0 0 0 bit 7: transmit pattern load (tc). a low-to-high transition loads the pattern generator with the pattern that is to be generated. this bit should be toggled from low to high whenever the host wishes to load a new pattern. must be cleared and set again for subsequent loads. bit 6: transmit invert-data enable (tinv) 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream bit 5: receive invert-data enable (rinv) 0 = do not invert the incoming data stream 1 = invert the incoming data stream bits 2 ? 4: pattern select bits (ps0 to ps2) ps 2 ps1 ps0 pattern definition 0 0 0 pseudorandom 2e7 - 1 0 0 1 pseudorandom 2e11 - 1 0 1 0 pseudorandom 2e15 - 1 0 1 1 pseudorandom pattern qrss. a 2 20 - 1 pattern with 14 consecutive zero restrictions. 1 0 0 repetitive pattern 1 0 1 alternating word pattern 1 1 0 modified 55 octet (daly) pattern. the daly pattern is a repeating 55 octet pattern that is byte-aligned into the active ds0 time slots. the pattern is defined in an atis (alliance for telecommunications industry solutions) committee t1 technical report number 25 (november 1993). 1 1 1 pseudorandom 2e9 ? 1 bit 1: load bit and error counters (lc). a low-to-high transition latches the current bit and error counts into registers tr.bbc1/ tr.bbc2/ tr.bbc3/ tr.bbc4 and tr.bec1/ tr.bec2/ tr.bec3 and clears the internal count. this bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. must be cleared and set again for subsequent loads. bit 0: force resynchronization (resync). a low-to-high transition forces the receive bert synchronizer to resynchronize to the incoming data stream. this bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. must be cl eared and set again for a subsequent resynchronization.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 287 of 338 register name: tr.bc2 register description: bert control register 2 register address: e1h bit # 7 6 5 4 3 2 1 0 name eib2 eib1 eib0 sbe rpl3 rpl2 rpl1 rpl0 default 0 0 0 0 0 0 0 0 bits 5 ? 7: error insert bits 0 to 2 (eib0 to eib2). automatically inserts bit errors at the prescribed rate into the generated data pattern. can be used for verifying error-detection features. bit 4: single bit-error insert (sbe). a low-to-high transition creates a single-bit error. must be cleared and set again for a subsequent bit error to be inserted. bits 0 ? 3: repetitive pattern length bit 3 (rpl0 to rpl3). rpl0 is the lsb and rpl3 is the msb of a nibble that describes how long the repetitive pattern is. the valid range is 17 (0000) to 32 (1111). these bits are ignored if the receive bert is programmed for a pseudorandom pattern. to create repetitive patterns fewer than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. for example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101). length (bits) rpl3 rpl2 rpl1 rpl0 17 0 0 0 0 18 0 0 0 1 19 0 0 1 0 20 0 0 1 1 21 0 1 0 0 22 0 1 0 1 23 0 1 1 0 24 0 1 1 1 25 1 0 0 0 26 1 0 0 1 27 1 0 1 0 28 1 0 1 1 29 1 1 0 0 30 1 1 0 1 31 1 1 1 0 32 1 1 1 1 eib2 eib1 eib0 error rate inserted 0 0 0 no errors automatically inserted 0 0 1 10e-1 0 1 0 10e-2 0 1 1 10e-3 1 0 0 10e-4 1 0 1 10e-5 1 1 0 10e-6 1 1 1 10e-7
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 288 of 338 register name: tr.bbc1 register description: bert bit count register 1 register address: e3h bit # 7 6 5 4 3 2 1 0 name bbc7 bbc6 bbc5 bbc 4 bbc3 bbc2 bbc1 bbc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert bit counter bits 0 to 7 (bbc0 to bbc7). bbc0 is the lsb of the 32-bit counter. register name: tr.bbc2 register description: bert bit count register 2 register address: e4h bit # 7 6 5 4 3 2 1 0 name bbc15 bbc14 bbc13 bbc 12 bbc11 bbc10 bbc9 bbc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert bit counter bits 8 to 15 (bbc8 to bbc15) register name: tr.bbc3 register description: bert bit count register 3 register address: e5h bit # 7 6 5 4 3 2 1 0 name bbc23 bbc22 bbc21 bbc 20 bbc19 bbc18 bbc17 bbc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert bit counter bits 16 to 23 (bbc16 to bbc23) register name: tr.bbc4 register description: bert bit count register 4 register address: e6h bit # 7 6 5 4 3 2 1 0 name bbc31 bbc30 bbc29 bbc 28 bbc27 bbc26 bbc25 bbc24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: bert bit counter bits 24 to 31 (bbc24 to bbc31). bbc31 is the msb of the 32-bit counter.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 289 of 338 register name: tr.bec1 register description: bert error-count register 1 register address: e7h bit # 7 6 5 4 3 2 1 0 name ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: error counter bits 0 to 7 (ec0 to ec7). ec0 is the lsb of the 24-bit counter. register name: tr.bec2 register description: bert error-count register 2 register address: e8h bit # 7 6 5 4 3 2 1 0 name ec15 ec14 ec13 ec 12 ec11 ec10 ec9 ec8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: error counter bits 8 to 15 (ec8 to ec15) register name: tr.bec3 register description: bert error-count register 3 register address: e9h bit # 7 6 5 4 3 2 1 0 name ec23 ec22 ec21 ec 20 ec19 ec18 ec17 ec16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: error counter bits 16 to 23 (ec16 to ec23). ec0 is the msb of the 24-bit counter.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 290 of 338 register name: tr.bic register description: bert interface control register register address: eah bit # 7 6 5 4 3 2 1 0 name ? rfus ? tbat tfus ? bertdir berten default 0 0 0 0 0 0 0 0 bit 6: receive framed/unframed select (rfus) 0 = bert is not sent data from the f-bit position (framed) 1 = bert is sent data from the f-bit position (unframed) bit 4: transmit byte-align toggle (tbat). a 0-to-1 transition forces the bert to byte align its pattern with the transmit formatter. this bit must be transitioned in order to byte align the daly pattern. bit 3: transmit framed/unframed select (tfus) 0 = bert does not source data into the f-bit position (framed) 1 = bert does source data into the f-bit position (unframed) bit 1: bert direction (bertdir) 0 = network bert transmits toward the network (ttip and tring) and receives from the network (rtip and rring). the bert pattern can be looped back to the receiver internally by using the framer loopback function. 1 = system bert transmits toward the system backplane (rsero) and receives from the system backplane (tseri). bit 0: bert enable (berten) 0 = bert disabled 1 = bert enabled
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 291 of 338 register name: tr.erc register description: error-rate control register register address: ebh bit # 7 6 5 4 3 2 1 0 name wnoe ? ? ce er3 er2 er1 er0 default 0 0 0 0 0 0 0 0 bit 7: write noe registers (wnoe). if the host wishes to update to the tr.noex registers, this bit must be toggled from a 0 to a 1 after the host has already loaded the prescribed error count into the tr.noex registers. the toggling of this bit causes the error count loaded into the tr.noex registers to be loaded into the error-insertion circuitry on the next clock cycle. subsequent updates require that the wnoe bit be set to 0 and then 1 once again. bit 4: constant errors (ce). when this bit is set high (and the er0 to er3 bits are not set to 0000), the error- insertion logic ignores the number-of-error registers (tr.noe1, tr.noe2) and generates errors constantly at the selected insertion rate. when ce is set to 0, the tr.noex registers determine how many errors are to be inserted. bits 0 ? 3: error-insertion rate select bits (er0 to er3) er3 er2 er1 er0 error rate 0 0 0 0 no errors inserted 0 0 0 1 1 in 16 0 0 1 0 1 in 32 0 0 1 1 1 in 64 0 1 0 0 1 in 128 0 1 0 1 1 in 256 0 1 1 0 1 in 512 0 1 1 1 1 in 1024 1 0 0 0 1 in 2048 1 0 0 1 1 in 4096 1 0 1 0 1 in 8192 1 0 1 1 1 in 16,384 1 1 0 0 1 in 32,768 1 1 0 1 1 in 65,536 1 1 1 0 1 in 131,072 1 1 1 1 1 in 262,144
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 292 of 338 register name: tr.noe1 register description: number-of-errors 1 register address: ech bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: number-of-errors counter bits 0 to 7 (c0 to c7). bit c0 is the lsb of the 10-bit counter. register name: tr.noe2 register description: number-of-errors 2 register address: edh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? c9 c8 default 0 0 0 0 0 0 0 0 bits 0 ? 1: number-of-errors counter bits 8 to 9 (c8 to c9). bit c9 is the msb of the 10-bit counter.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 293 of 338 11.7.1 number-of-errors left register the host can read the tr.noelx registers at any time to determine how many errors are left to be inserted. register name: tr.noel1 register description: number-of-errors left 1 register address: eeh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: number-of-errors left counter bits 0 to 7 (c0 to c7). bit c0 is the lsb of the 10-bit counter. register name: tr.noel2 register description: number-of-errors left 2 register address: efh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? c9 c8 default 0 0 0 0 0 0 0 0 bits 0 ? 1: number-of-errors left counter bits 8 to 9 (c8 to c9). bit c9 is the msb of the 10-bit counter.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 294 of 338 12 functional timing 12.1 functional serial i/o timing the serial interface provides flexible timing to interconnect with a wide variety of serial interfaces. tden is an input signal that can be used to enable or block the tsero data. the ?shaded bits? are not clocked by the DS33R11. the tden must occur one bit before the effected bit in the tsero stream. note that polarity of the tden is selectable through li.tslcr. in the figure below, tden is ac tive low, allowing the bits to clock and inactive high, causing the next data bit not be clocked. tclke can be gapped as shown in the following figure. similarly, the receiver function is governed by rclki, rden and rseri. r seri data will not be provided to the receiver for the bits blocked when rden is inactive. the rden polarity can be programmed by li.rslcr . the rden signal must be coincident with the rseri bit that needs to be blocked. figure 12-1. tx serial interface functional timing tclk gapped tser tclke tden tsero tclke gapped tsero figure 12-2. rx serial interface functional timing tser rclki rden rseri rclki gapped rseri
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 295 of 338 the DS33R11 provides the tbsync signal as a byte boundary indication to an external interface when x.86 (laps) functionality is selected. the functional timing of tbsync is shown in the following figure.tbsync is active high on the last bit of the byte being shifted out, and occurs every 8 bits. for the serial receiver interface, rbsync is used to provide byte boundary indication to the ds33r 11 when x.86 (laps) mode is used. the functional timing is shown in figure 12-3 . in x.86 mode, the receiver expects the rbsync byte indicator as shown in figure 12-4 . figure 12-3. transmit byte sync functional timing last bit 1st bit tclke tbysync tsero figure 12-4. receive byte sync functional timing last bit 1st bit rclki rbysync rseri 12.2 mii and rmii interfaces the mii interface transmit port has its own tx_clk and data interface. the data txd [3:0] operates synchronously with tx_clk. the lsb is presented first. tx_clk should be 2.5mhz for 10mbit/s operation and 25mhz for 100mbit/s operation. tx_en is valid at the same time as the first byte of the preamble. in dte mode tx_clk is input from the external phy. in dce mode, the DS33R11 provides tx_clk, derived from an external reference (sysclki). figure 12-5. mii transmit functional timing txd[3:0] tx_en tx_clk p r e a e m b l e f c s
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 296 of 338 in half-duplex (dte) mode, the DS33R11 supports crs and col signals. crs is active when the phy detects transmit or receive activity. if there is a collision as indicated by the col input, the DS33R11 will replace the data nibbles with jam nibbles. after a ?random? time interval, the packet is retransmitted. the mac will try to send the packet a maximum of 16 times. the jam sequence consists of 55555555h. note that the col signal and crs can be asynchronous to the tx_clk and are only valid in half duplex mode. figure 12-6. mii transmit half d uplex with a collision functional timing txd[3:0] tx_en tx_clk p r e a m b l e j j j j j j j j crs col receive data (rxd[3:0]) is clocked from the external phy synchronously with rx_clk. the rx_clk signal is 2.5mhz for 10mbit/s operation and 25mhz for 100mbit/s operation. rx_dv is asserted by the phy from the first nibble of the preamble in 100 mbit/s operation or first nibbl e of sfd for 10 mbit/s operation. the data on rxd[3:0] is not accepted by the mac if rx_dv is low or rx_err is high (in dte mode). rx_err should be tied low when in dce mode. figure 12-7. mii receive functional timing rxd[3:0] rx_clk p r e a e m b l e f c s in rmii mode, tx_en is high with the first bit of the preamble. the txd[1:0] is synchronous with the 50mhz ref_clk. for 10 mbit/s operation, the data bit outputs are updated every 10 clocks . figure 12-8. rmii transmit interface functional timing txd[1:0] tx_en refclk p r e a m b l e f c s
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 297 of 338 rmii receive data on rxd[1:0] is expected to be synchronous with the rising edge of the 50 mhz ref_clk. the data is only valid if crs_dv is high. the external phy asynchronously drives crs_dv low during carrier loss. figure 12-9. rmii receive interface functional timing rxd[1:0] crs_dv refclk p r e a m b l e f c s 12.3 transceiver t1 mode functional timing figure 12-10. receive-side d4 timing figure 12-11. receive-side esf timing frame# 1 2345678910111212345 3 rsync 1 rsync rfsync 2 rsync note 1: rsync in the frame mode (tr.iocr1.5 = 0) and double-wide frame sync is not enabled (tr.iocr1.6 = 0). note 2: rsync in the frame mode (tr.iocr1.5 = 0) and double-wide frame sync is enabled (tr.iocr1.6 = 1). note 3: rsync in the multiframe mode (tr.iocr1.5 = 1). 123456789101112 1 2 3 rfsync frame# rsync rsync rsync 13141516171819202122232412345 note 1: rsync in frame mode (tr.iocr1.4 = 0) and double-wide frame sync is not enabled (tr.iocr1.6 = 0). note 2: rsync in frame mode (tr.iocr1.4 = 0) and double-wide frame sync is enabled (tr.iocr1.6 = 1). note 3: rsync in multiframe mode (tr.iocr1.4 = 1).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 298 of 338 figure 12-12. receive-side boundary timing (elastic store disabled) figure 12-13. receive-side 1.544mhz bounda ry timing (elastic store enabled) channel 23 channel 24 channel 1 channel 23 channel 24 channel 1 rclko rsero rsync rfsync rsig rchclk rchblk 1 b a c/a d/b a c/a d/b lsb f msb msb lsb ab note 1: rchblk is programmed to block channel 24. rsero channel 23 channel 24 channel 1 rchclk rchblk rsysclk rsync 2 3 rsync 1 rmsync rsig lsb f msb msb lsb channel 23 channel 24 channel 1 b a c/a d/b a c/a d/b ab note 1: rsync is in the output mode (tr.iocr1.4 = 0). note 2: rsync is in the input mode (tr.iocr1.4 = 1). note 3: rchblk is programmed to block channel 24.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 299 of 338 figure 12-14. receive-side 2.048mhz bounda ry timing (elastic store enabled) figure 12-15. transmit-side d4 timing rser o channel 1 rchclk rchblk rsysclk rsync channel 31 channel 32 1 3 4 rsync 2 rmsync rsig channel 31 channel 32 b a c/a d/b c/a d/b ab channel 1 lsb msb lsb f 5 note 1: rsero data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1. note 2: rsync is in the output mode (tr.iocr1.4 = 0). note 3: rsync is in the input mode (tr.iocr1.4 = 1). note 4: rchblk is forced to 1 in the same channels as rsero (see note 1). note 5: the f-bit position is passed through the receive-side elastic store. 12345678910111212345 1 2 3 tssync frame# tsync tsync tsync note 1: tsync in the frame mode (tr.iocr1.2 = 0) and double-wide frame sync is not enabled (tr.iocr1.1 = 0). note 2: tsync in the frame mode (tr.iocr1.2 = 0) and double-wide frame sync is enabled (tr.iocr1.1 = 1). note 3: tsync in the multiframe mode (tr.iocr1.2 = 1).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 300 of 338 figure 12-16. transmit-side esf timing figure 12-17. transmit-side boundary ti ming (with elastic store disabled) 123456789101112 1 2 3 tssync frame# tsync tsync tsync 13141516171819202122232412345 note 1: tsync in frame mode (tr.iocr1.2 = 0) and double-wide frame sync is not enabled (tr.iocr1.3 = 0). note 2: tsync in frame mode (tr.iocr1.2 = 0) and double-wide frame sync is enabled (tr.iocr1.3 = 1). note 3: tsync in multiframe mode (tr.iocr1.2 = 1). lsb f msb lsb msb lsb msb channel 1 channel 2 channel 1 channel 2 abc/ad/b abc/ad/b tclkt tseri tsync tsync tsig tchclk tchblk d/b 1 2 3 note 1: tsync is in the output mode (tr.iocr1.1 = 1). note 2: tsync is in the input mode (tr.iocr1.1 = 0). note 3: tchblk is programmed to block channel 2.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 301 of 338 figure 12-18. transmit-side 1.544mhz bounda ry timing (elastic store enabled) figure 12-19. transmit-side 2.048mhz bounda ry timing (elastic store enabled) lsb f msb lsb msb channel 1 channel 24 abc/ad/b abc/ad/b tsysclk tseri tssync tsig tchclk tchblk channel 23 a channel 23 channel 24 channel 1 1 note 1: tchblk is programmed to block channel 24 (if the tpcsi bit is set, then the signaling data at tsig is ignored during channel 24). lsb f lsb msb channel 1 channel 32 abc/ad/b abc/ad/b tsysclk tseri tssync tsig tchclk tchblk channel 31 a channel 31 channel 32 channel 1 1 4 2,3 note 1: tseri data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. note 2: tchblk is programmed to block channel 31 (if the tpcsi bit is set, then the signaling data at tsig will be ignored). note 3: tchblk is forced to 1 in the same channels as tseri is ignored (see note 1). note 4: the f-bit position for the t1 frame is sampled and passed through the transmit-side elastic store into the msb bit position of channel 1. (normally, the transmit-side formatter overwrites the f-bit position unless the formatter is programmed to pass through the f-bit position.)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 302 of 338 12.4 e1 mode figure 12-20. receive-side timing figure 12-21. receive-side boundary ti ming (with elastic store disabled) frame# 1 23456789101112131415161 rsync 1 rsync rfsync 2 note 1: rsync in frame mode (tr.iocr1.5 = 0). note 2: rsync in multiframe mode (tr.iocr1.5 = 1). note 3: this diagram assumes the cas mf begins in the raf frame. channel 32 channel 1 channel 2 channel 32 channel 1 channel 2 rclko rsero rsync rfsync rsig rchclk rchblk 1 cd a lsb msb ab si 1 a sa4 sa5 sa6 sa7 sa8 b note 4 note 1: rchblk is programmed to block channel 1. note 2: shown is a rnaf frame boundary. note 3: rsig normally contains the cas multiframe alignment nibble (0000) in channel 1.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 303 of 338 figure 12-22. receive-side boundary timing, rsysclk = 1.544mhz (e-store enabled) figure 12-23. receive-side boundary timing, rsysclk = 2.048mhz (e-store enabled) rsero channel 23/31 channel 24/32 channel 1/2 rchclk rchblk rsysclk rsync 2 3 rsync 1 rmsync lsb f msb msb lsb 4 note 1: data from the e1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the e1 link is mapped to channel 1 of the t1 link, etc.) and the f-bit position is added (forced to on 1). note 2: rsync in the output mode (tr.iocr1.4 = 0). note 3: rsync in the input mode (tr.iocr1.4 = 1). note 4: rchblk is programmed to block channel 24. rsero channel 1 rchclk rchblk rsysclk rsync channel 31 channel 32 1 3 rsync 2 rmsync rsig channel 31 channel 32 c d ab channel 1 lsb msb lsb msb c d b a note 4 note 1: rsync is in the output mode (tr.iocr1.4 = 0). note 2 : rsync is in the input mode (tr.iocr1.4 = 1). note 3: rchblk is programmed to block channel 1. note 4: rsig normally contains the cas multiframe alignment nibble (0000) in channel 1.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 304 of 338 figure 12-24. g.802 timing, e1 mode only figure 12-25. transmit-side timing 12345678910111213141516171819202122232425262728293031 0 31 32 ts # rsync tsync rchclk tchclk rchblk tchblk channel 26 channel 25 lsb msb rclko / rsysclk tclkt / tsysclk rsero / tseri rchclk / tchclk rchblk / tchblk 12 0 note: rchblk or tchblk programmed to pulse high during time slots 1 through 15, 17 through 25, and bit 1 of time slot 26. 12345 678910 11 12 1 tssync frame# tsync tsync 13 14 15 16 12345 14 15 16 678910 2 note 1: tsync in frame mode (tr.iocr1.2 = 0). note 2: tsync in multiframe mode (tr.iocr1.2 = 1). note 3: this diagram assumes both the cas mf and the crc4 mf begin with the taf frame.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 305 of 338 figure 12-26. transmit-side boundary timing (elastic store disabled) figure 12-27. transmit-side boundary timing, tsysclk = 1.544mhz (elastic store enabled) lsb msb lsb msb channel 1 channel 2 channel 1 channel 2 abcd tclkt tseri tsync tsync tsig tchclk tchblk 1 2 3 si 1 a sa4 sa5 sa6 sa7 sa8 d note 1: tsync is in the output mode (tr.iocr1.1 = 1). note 2: tsync is in the input mode (tr.iocr1.1 = 0). note 3: tchblk is programmed to block channel 2. note 5: the signaling data at tsig during channel 1 is normally overwritten in the transmit formatter with the cas mf alignment nibble (0000). note 6: shown is a tnaf frame boundary. lsb f msb lsb msb channel 1 channel 24 tsysclk tseri tssync tchclk tchblk channel 23 1 2 note 1: the f-bit position in the tseri data is ignored. note 2: tchblk is programmed to block channel 24.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 306 of 338 figure 12-28. transmit-side boundary timi ng, tsysclk = 2.048mhz (elastic store enabled) lsb f lsb msb channel 1 channel 32 a b c d a b tsysclk tseri tssync tsig tchclk tchblk channel 31 a channel 31 channel 32 channel 1 1 4 c d note 1: tchblk is programmed to block channel 31.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 307 of 338 13 operating parameters absolute maximum ratings voltage range on any lead with respect to v ss (except v dd )?????????????????..-0.5v to +5.5v supply voltage (vdd3.3) range with respect to v ss ?????????????????????.-0.3v to +3.6v supply voltage (vdd1.8) with respect to v ss ????????????.????????????.-0.3v to +2.0v ambient operating temperatur e range????????????????????????? ......-40c to +85c junction operating temperat ure range??????????????????????????- 40c to +125c storage temperature ra nge???????????????????????????????-55c to +125c soldering temperature ??????????????????????..see ipc/jedec j-st d-020 specification these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. ambient operating temperature range is assuming the device is mounted on a jedec standard test board in a convection cooled jed ec test enclosure. note: the ?typ? values listed below are not production tested. table 13-1. recommended dc operating conditions (vdd3.3 = 3.3v  5%, vdd1.8 = 1.8v  5%, t j = -40c to +85c.) parameter symbol conditions min typ max units logic 1 v ih 2.35 3.465 v logic 0 v il -0.3 +0.75 v supply (vdd3.3) 5% vdd3.3 3.135 3.300 3.465 v supply (vdd1.8) 5% vdd1.8 1.71 1.8 1.89 v table 13-2. dc electrical characteristics (vdd3.3 = 3.3v  5%, vdd1.8 = 1.8v  5%, t j = -40c to +85c.) parameter symbol conditions min typ max units i/o supply current (vdd3.3 = 3.465v) i ddio (notes 1, 2) 100 ma core supply current (vdd1.8 = 1.89v) i ddcore (notes 1, 2) 30 ma lead capacitance c io (note 3) 7 pf i il -10 +10 input leakage i ilp -50 -10  a output leakage (when high-z) i lo -10 +10  a (i oh = -4.0ma) v oh all outputs 2.35 (i ol = +4.0ma) v ol all outputs 0.75 (i oh = -8.0ma) v oh ref_clko 2.35 output voltage (i ol = +12.0ma) v ol tsero 0.75 v v il 0.75 input voltage v ih 2.35 v note 1: typical power consumption is approximately 400mw. note 2: all outputs loaded with rated capacitance; all inputs between v dd and v ss ; inputs with pullups connected to v dd . note 3: value guaranteed by design (gbd).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 308 of 338 13.1 thermal characteristics table 13-3. thermal characteristics parameter min typ max ambient temperature (note 1) -40c +85c junction temperature (note 2) +125c theta-ja (  ja ) in still air for 256-pin 27mm bga (notes 2, 3) +20.3c/w note 1: the package is mounted on a four-layer jedec standard test board. note 2: value guaranteed by design (gbd). note 3: theta-ja (  ja ) is the junction to ambient thermal resistance, when the package is mounted on a four-layer jedec standard test board. table 13-4. theta-ja vs. airflow air flow theta-ja 256-pin (27mm) bga 0m/s (note 1) 20.3c/w 1m/s (note 1) 17.9c/w 2.5m/s (note 1) 16.9c/w note 1: value guaranteed by design (gbd).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 309 of 338 13.2 mii interface table 13-5. transmit mii interface (note 1, figure 13-1 ) 10mbps 100mbps parameter symbol min typ max min typ max units tx_clk period t1 400 40 ns tx_clk low time t2 140 260 14 26 ns tx_clk high time t3 140 260 14 26 ns tx_clk to txd, tx_en delay t4 0 20 0 20 ns note 1: timing parameters in this table are guaranteed by design (gbd). figure 13-1. transmit mii interface timing tx_clk txd[3:0] tx_en t4 t4 t2 t3 t1
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 310 of 338 table 13-6. receive mii interface (note 1, figure 13-2 ) 10mbps 100mbps parameter symbol min typ max min typ max units rx_clk period t5 400 40 ns rx_clk low time t6 140 260 14 26 ns rx_clk high time t7 140 260 14 26 ns rxd, rx_dv to rx_clk setup time t8 5 5 ns rx_clk to rxd, rx_dv hold time t9 5 5 ns note 1: timing parameters in this table are guaranteed by design (gbd). figure 13-2. receive mii interface timing t8 t9 rx_clk rxd[3:0] rx_dv t8 t9 t5 t6 t7
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 311 of 338 13.3 rmii interface table 13-7. transmit rmii interface (note 1, figure 13-3 ) 10mbps 100mbps parameter symbol min typ max min typ max units ref_clk frequency 50mhz 50ppm 50mhz 50ppm ref_clk period t1 20 20 ns ref_clk low time t2 7 13 7 13 ns ref_clk high time t3 7 13 7 13 ns ref_clk to txd, tx_en delay t4 5 10 5 10 ns note 1: timing parameters in this table are guaranteed by design (gbd). figure 13-3. transmit rmii interface timing ref_clk txd[1:0] tx_en t4 t4 t2 t3 t1
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 312 of 338 table 13-8. receive rmii interface (note 1, figure 13-4 ) 10mbps 100mbps parameter symbol min typ max min typ max units ref_clk frequency 50mhz 50ppm 50mhz 50ppm mhz ref_clk period t1 20 20 ns ref_clk low time t2 7 13 7 13 ns ref_clk high time t3 7 13 7 13 ns rxd, crs_dv to ref_clk setup time t8 5 5 ns ref_clk to rxd, crs_dv hold time t9 5 5 ns note 1: timing parameters in this table are guaranteed by design (gbd). figure 13-4. receive rmii interface timing t8 t9 ref_clk rxd[3:0] crs_dv t8 t9 t5 t6 t7
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 313 of 338 13.4 mdio interface table 13-9. mdio interface (note 1, figure 13-5 ) parameter symbol min typ max units mdc frequency 1.67 mhz mdc period t1 540 600 660 ns mdc low time t2 270 300 330 ns mdc high time t3 270 300 330 ns mdc to mdio output delay t4 20 10 ns mdio setup time t5 10 ns mdio hold time t6 20 ns note 1: timing parameters in this table are guaranteed by design (gbd). figure 13-5. mdio interface timing mdc mdio t4 mdc t2 t3 t1 mdio t5 t6
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 314 of 338 13.5 transmit wan interface table 13-10. transmit wan interface (note 1, figure 13-6 ) parameter symbol min typ max units tclke frequency 52 mhz tclke period t1 19.2 ns tclke low time t2 8 ns tclke high time t3 8 ns tclke to tsero output delay t4 3 10 ns tbsync setup time t5 7 ns tbsync hold time t6 7 ns tclke to tden output delay t7 3.5 ns note 1: timing parameters in this table are guaranteed by design (gbd). figure 13-6. transmit wan interface timing tclke t2 t3 t1 tsero t4 tbsync t5 t6 tden t7
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 315 of 338 13.6 receive wan interface table 13-11. receive wan interface (note 1, figure 13-7 ) parameter symbol min typ max units rclki frequency 52 mhz rclki period t1 19.2 ns rclki low time t2 8 ns rclki high time t3 8 ns rseri setup time t4 7 ns rden setup time t4 7 ns rbsync setup time t4 7 ns rden setup time t4 7 ns rbsync setup time t4 7 ns rseri hold time t5 2 ns rbsync hold time t5 2 ns rden hold time t5 2 ns rbsync hold time t5 2 ns note 1: timing parameters in this table are guaranteed by design (gbd). figure 13-7. receive wan interface timing rclki t2 t3 t1 rseri rden t4 t5 t4 t5 rbsync t4 t5
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 316 of 338 13.7 sdram timing table 13-12. sdram interface timing (note 1, figure 13-8 ) 100 mhz parameter symbol min typ max units sdclko period t1 9.7 10 10.3 ns sdclko duty cycle t2 4 6 ns sdclko to sdata valid write to sdram t3 7 ns sdclko to sdata drive on write to sdram t4 4 ns sdclko to sdata invalid write to sdram t5 3 ns sdclko to sdata drive off write to sdram t6 4 ns sdata to sdclko setup time read from sdram t7 2 ns sdclko to sdata hold time read from sdram t8 2 ns sdclko to sras , scas , swe , sdcs active read or write to sdram t9 5 ns sdclko to sras , scas , swe , sdcs inactive read or write to sdram t10 2 ns sdclko to sda, sba valid read or write to sdram t11 7 ns sdclko to sda, sba invalid read or write to sdram t12 2 ns sdclko to sdmask valid read or write to sdram t13 5 ns sdclko to sdmask invalid read or write to sdram t14 2 ns note 1: timing parameters in this table are guaranteed by design (gbd).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 317 of 338 figure 13-8. sdram interface timing sdclko (output) sdata (output) t1 sdata (input) sras, scas, swe, sdcs (output) t2 t3 t5 t6 t7 t8 t10 t9 sda, sba (output) sdmask (output) t4 t12 t11 t14 t13
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 318 of 338 13.8 microprocessor bus ac characteristics table 13-13. ac characteristics?microprocessor bus timing (vdd3.3 = 3.3v  5%, vdd1.8 = 1.8v  5%, t j = -40c to +85c.) (note 1, figure 13-9 , figure 13-10 , figure 13-11 , and figure 13-12 ) parameter symbol min typ max units setup time for a[12:0] valid to cs active t1 0 ns setup time for cs active to either rd or wr active t2 0 ns delay time from either rd or ds active to data[7:0] valid t3 75 ns hold time from either rd or wr inactive to cs inactive t4 0 ns hold time from cs or rd or ds inactive to data[7:0] tri-state t5 5 20 ns wait time from r w active to latch data t6 80 ns data set up time to ds active t7 10 ns data hold time from r w inactive t8 2 ns address hold from r w inactive t9 0 ns write access to subsequent write/read access delay time t10 80 ns note 1: timing parameters in this table are guaranteed by design (gbd).
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 319 of 338 figure 13-9. intel bus read timing (modec = 00) t2 t3 address valid data valid t4 t9 t5 t10 addr[12:0] data[7:0] cs rd wr t1 figure 13-10. intel bus write timing (modec = 00) t2 t6 address valid t4 t9 t10 addr[12:0] data[7:0] rd wr t7 t8 t1 cs/cst
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 320 of 338 figure 13-11. motorola bus read timing (modec = 01) t2 t3 address valid data valid t4 t9 t5 t10 addr[12:0] data[7:0] ds rw t1 cs/cst figure 13-12. motorola bus write timing (modec = 01) t2 t6 address valid t4 t9 t10 addr[12:0] data[7:0] rw ds t7 t8 t1 cs/cst
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 321 of 338 13.9 ac characteristics: receive-side table 13-14. ac characteristics: receive side (v dd = 3.3v  5%, t a = -40c to +85c.) (note 1, figure 13-3 , figure 13-14 , and figure 13-15 ) parameter symbol conditions min typ max units 488 (e1) rdclko period t lp 648 (t1) ns t lh (note 2) 200 0.5 t lp rdclko pulse width t ll (note 2) 200 0.5 t lp ns t lh (note 3) 150 0.5 t lp rdclko pulse width t ll (note 3) 150 0.5 t lp ns 488 (e1) rdclki period t cp 648 (t1) ns t ch 20 0.5 t cp rdclki pulse width t cl 20 0.5 t cp ns (note 4) 648 rsysclk period t sp (note 5) 488 ns t sh 20 0.5 t sp ns rsysclk pulse width t sl 20 0.5 t sp ns rsync setup to rsysclk falling t su 20 ns rsync pulse width t pw 50 ns rposi/rnegi setup to rdclki falling t su 20 ns rposi/rnegi hold from rdclki falling t hd 20 ns rsysclk, rdclki rise and fall times t r , t f 22 ns delay rdclko to rp oso, rnego valid t dd 50 ns delay rclko to rsero, rdata, rsig valid t d1 50 ns delay rclko to rchclk, rsync, rchblk, rfsync t d2 50 ns delay rsysclk to rsero, rsig valid t d3 22 ns delay rsysclk to rchclk, rchblk, rmsync, rsync t d4 22 ns note 1: timing parameters in this table are guaranteed by design (gbd). note 2: jitter attenuator enabled in the receive path. note 3: jitter attenuator disabled or enabled in the transmit path. note 4: rsysclk = 1.544mhz. note 5: rsysclk = 2.048mhz.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 322 of 338 figure 13-13. receive-side timing t d1 1 t d2 rsero / rdata / rsig rchclk rchblk rsync rclko rfsync / rmsync t d2 t d2 t d2 1st frame bit note 1: rsync is in the output mode. note 2: no relationship between rchclk and rchblk and other signals is implied.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 323 of 338 figure 13-14. receive-side timing, elastic store enabled f t t r t d3 t d4 t d4 t d4 t t su hd rsero / rsig rchclk rchblk 1 rsync 2 rsync rsysclk sl t t sp sh t t d4 rmsync see note 3 note 1: rsync is in the output mode. note 2: rsync is in the input mode. note 3: f-bit when mstrreg.1 = 0, msb of ts0 when mstreg.1 = 1.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 324 of 338 figure 13-15. receive line interface timing t f t r rposi, rnegi rdclki cl t t cp ch t t su t hd t dd rposo, rnego rdclko ll t t lp lh t
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 325 of 338 13.10 ac characteristics: backplane clock timing table 13-15. ac characteristics: backplane clock synthesis (v dd = 3.3v  5%, t a = -40c to +85c.) (note 1, ( figure 13-16 ) parameter symbol conditions min typ max units delay rclko to bpclk t d1 10 ns note: timing parameters in this table are guaranteed by design (gbd). figure 13-16. receive timing delay rclko to bpclk t d1 bpclk rclko note: if rclko is 1.544 mhz, bpclk will be asynchronous.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 326 of 338 13.11 ac characteristics: transmit side table 13-16. ac characteristics: transmit side (v dd = 3.3v  5%, t a = 0c to +85c.) (note 1, figure 13-17 , figure 13-18 , and figure 13-19 ) parameter symbol conditions min typ (e1) max units 488 (e1) tclkt period t cp 648 (t1) ns t ch 20 0.5 t cp tclkt pulse width t cl 20 0.5 t cp ns 488 (e1) tdclki period t lp 648 (t1) ns t lh 20 0.5 t lp tdclki pulse width t ll 20 0.5 t lp ns (note 2) 648 tsysclk period t sp (note 3) 448 ns 20 0.5 t sp tsysclk pulse width t sp 20 0.5 t sp ns tsync or tssync setup to tclkt or tsysclk falling t su 20 ns tsync or tssync pulse width t pw 50 ns tseri, tsig, tdata, tposi, tnegi setup to tclkt, tsysclk, tdclki falling t su 20 ns tseri, tsig, tdata hold from tclkt or tsysclk falling t hd 20 ns tposi, tnegi hold from tdclki falling t hd 20 ns tclkt, tdclki or tsysclk rise and fall times t r , t f 25 ns delay tclko to tposo, tnego valid t dd 50 ns delay tclkt to teso, ut-utdo valid t d1 50 ns delay tclkt to tchblk, tchclk, tsync t d2 50 ns delay tsysclk to tchclk, tchblk t d3 22 ns note 1: timing parameters in this table are guaranteed by design (gbd). note 2: tsysclk = 1.544mhz. note 3: tsysclk = 2.048mhz.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 327 of 338 figure 13-17. transmit-side timing t f t r 1 tclkt tseri / tsig / tdata tchclk t t cl t ch cp tsync tsync tlink tlclk tchblk t d2 t d2 t d2 t t t t t t hd su d2 su hd d1 t hd 2 5 teso t su note 1: tsync is in the output mode (iocr1.1 = 1). note 2: tsync is in the input mode (iocr1.1 = 0). note 3: tseri is sampled on the falling edge of tclkt when the transmit-side elastic store is disabled. note 4: tchclk and tchblk are synchronous with tclkt when the transmit-side elastic store is disabled.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 328 of 338 figure 13-18. transmit-side timing, elastic store enabled figure 13-19. transmit line interface timing tdclko tposo, tnego t dd t f t r tdclki tposi, tnegi t t ll t lh lp t hd t su t f t r tsysclk tseri tchclk t t sl t sh sp tssync tchblk t d3 t d3 t t t su hd su t hd note 1: tseri is only sampled on the falling edge of tsysclk when the transmit-side elastic store is enabled. note 2: tchclk and tchblk are synchronous with tsysclk when the transmit-side elastic store is enabled.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 329 of 338 13.12 jtag interface timing table 13-17. jtag interface timing (vdd3.3 = 3.3v  5%,vdd1.8 = 1.8v  5%, t j = -40c to +85c.) (note 1, figure 13-20 ) parameter symbol min typ max units jtclk clock period t1 1000 ns jtclk clock high:low time (note 2) t2 : t3 50 500 ns jtclk to jtdi, jtms setup time t4 2 ns jtclk to jtdi, jtms hold time t5 2 ns jtclk to jtdo delay t6 2 50 ns jtclk to jtdo hiz delay t7 2 50 ns jtrst width low time t8 100 ns note 1: timing parameters in this table are guaranteed by design (gbd). note 2: clock can be stopped high or low figure 13-20. jtag interface timing diagram jtclk t1 jtd0 t4 t5 t2 t3 t7 jtdi, jtms t6 jtrst t8
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 330 of 338 14 jtag information the DS33R11 contains two jtag ports. port 1 is for the ethernet mapper, and port 2 is for the t1/e1/j1 transceiver. the device supports the standard instruc tion codes sample:preload, bypass, and extest. optional public instructions included are highz, clamp, and idcode. see table 20-1. the ds26521 contains the following as required by ieee 1149.1 standard test access port and boundary scan architecture. test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the test access port has the necessary interface pins: jtrst , jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details. refer to ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994 for details about the boundary scan architecture and the test access port. figure 14-1. jtag functional block diagram boundary scan register identification register bypass register instruction register test access port controller mux select tri-state jtdi 10k jtms 10k jtclk jtrst 10k jtdo
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 331 of 338 14.1 jtag tap controller state machine description this section covers the details on the operation of the test access port (tap) controller state machine. the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. tap controller state machine the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. see figure 14-2 for a diagram of the state machine operation. test-logic-reset upon power up, the tap controller is in the test-logic-r eset state. the instruction register will contain the idcode instruction. all system logic of the device will operate normally. run-test-idle the run-test-idle is used between scan operations or during specific tests. the instruction register and test registers will remain idle. select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and will initiate a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir-scan state. capture-dr data may be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of jtcl k, the controller will go to the shift-dr state if jtms is low or it will go to the exit1-dr state if jtms is high. shift-dr the test data register selected by the current instruc tion is connected between jtdi and jtdo and will shift data one stage towards its serial output on each rising edge of jtcl k. if a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. exit1-dr while in this state, a rising edge on jtclk will put the c ontroller in the update-dr stat e, which terminates the scanning process, if jtms is high. a rising edge on jtcl k with jtms low will put the controller in the pause- dr state. pause-dr shifting of the test registers is halted w hile in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in t his state while jtms is low. a rising edge on jtclk with jtms high will put the contr oller in the exit2-dr state. exit2-dr a rising edge on jtclk with jtms high while in this st ate will put the controller in the update-dr state and terminate the scanning process. a rising edge on jtclk with jtms low will enter the shift-dr state.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 332 of 338 update-dr a falling edge on jtclk while in the update-dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the par allel output due to changes in the shift register. select-ir-scan all test registers retain their previous state. the instr uction register will remain unchanged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture-ir st ate and will initiate a scan sequence for the instruction register. jtms high dur ing a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir the capture-ir state is used to load the shift register in t he instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, t he controller will enter the exit1-ir state. if jtms is low on the rising edge of jt clk, the controller will enter the shift-ir state. shift-ir in this state, the shift register in the instruction r egister is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk towards the serial output. the parallel register, as well as all test registers, remains at their previous states. a rising edge on jtclk with jtms high will move the controller to the exit1-ir state. a rising edge on jtclk with jtms low will keep the controller in the shift-ir state while moving data one stage thorough the instruction shift register. exit1-ir a rising edge on jtclk with jtms low will put the controller in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller will enter the u pdate-ir state and terminate the scanning process. pause-ir shifting of the instruction shift register is halted temporar ily. with jtms high, a rising edge on jtclk will put the controller in the exit2-ir state. t he controller will remain in the pause-ir state if jtms is low during a rising edge on jtclk. exit2-ir a rising edge on jtclk with jtms low will put the controller in the update-ir state. the controller will loop back to shift-ir if jtms is high during a rising edge of jtclk in this state. update-ir the instruction code shifted into the instruction shift r egister is latched into the par allel output on the falling edge of jtclk as the controller enters this stat e. once latched, this instruction becom es the current instruction. a rising edge on jtclk with jtms held low will put the controller in the run-test-idle state. with jtms high, the controller will enter the select-dr-scan state.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 333 of 338 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0 figure 14-2. tap controller state diagram 14.2 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruct ion shift register is connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low will shift the data one st age towards the serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the exit2-ir st ate with jtms high will move the controller to the update-ir state. the falling edge of that same jtclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the ds26521 and its respective operational binary codes are shown in table 14-1 .
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 334 of 338 table 14-1. instruction codes for ieee 1149.1 architecture instruction selected regi ster instruction codes sample:preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 sample:preload this is a mandatory instruction for the ieee 1149.1 specif ication. this instruction supports two functions. the digital i/os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture- dr state. sample:preload also allows the device to shift data into the boundary scan register via jtdi using the shift-dr state. bypass when the bypass instruction is latched into the parallel instr uction register, jtdi connects to jtdo through the one-bit bypass test register. this allows data to pass fr om jtdi to jtdo not affecting the device?s normal operation. extest this allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled via t he update-ir state, the par allel outputs of all digital output pins are driven. the boundary scan register is connect ed between jtdi and jtdo. the capture-dr will sample all digital inputs into the boundary scan register. clamp all digital outputs of the device will output data from the boundary scan par allel output while connecting the bypass register between jtdi and jtdo. the outputs will not change during the clamp instruction. highz all digital outputs of the device are placed in a high-impedance state. the bypass register is connected between jtdi and jtdo. idcode when the idcode instruction is latc hed into the parallel instruction register, the identification test register is selected. the device identification code is loaded into t he identification register on the rising edge of jtclk following entry into the capture-dr state. shift-dr can be us ed to shift the identification code out serially via jtdo. during test-logic-reset, the identification code is forced into the instruction register?s parallel output. the id code will always have a ?1? in the lsb position. the next 11 bit s identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 335 of 338 14.3 jtag id codes table 14-2. id code structure device revision id[31:28] device code id[27:12] manufacturer?s code id[11:1] required id[0] ethernet mapper 0000 0000 0000 0110 0001 000 1010 0001 1 t1/e1/j1 transceiver 0000 0000 0000 0001 0000 000 1010 0001 1 14.4 test registers ieee 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. an optional test register has been included with the ds26521 design. this test register is the identification register and is used in conjunction with the idcode instruction and the test-logic-reset state of the tap controller. 14.4.1 boundary scan register this register contains both a shift register path and a lat ched parallel output for all control cells and digital i/o cells and is n bits in length. 14.4.2 bypass register this is a single one-bit shift register used in conjunction with the bypass, clamp, and highz instructions, which provides a short path between jtdi and jtdo. 14.4.3 identification register the identification register contains a 32-bit shift register and a 32-bit latched parallel output. this register is selected during the idcode instruction and when the tap cont roller is in the test-logic-reset state.
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 336 of 338 14.5 jtag functional timing this functional timing for the jtag circuits shows:  the jtag controller starting from reset state.  shifting out the first 4 lsb bits of the idcode.  shifting in the bypass instruction (111) w hile shifting out the mandatory x01 pattern.  shifting the tdi pin to the tdo pin through the bypass shift register.  an asynchronous reset occurs while shifting. figure 14-3. jtag functional timing jtclk jtrst jtms jtdi jtdo (state) reset x run test idle select dr scan capture dr shift dr exit1 dr update dr select dr scan select ir scan capture ir shift ir exit1 ir update ir select dr scan capture dr shift dr test logic idle (inst) idcode bypass idcode x x x x x output pin output pin level change if in "extest" instruction mode
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 337 of 338 15 package information (the package drawing(s) in this data sheet may not reflect t he most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) 15.1 package outline drawing of 256-bga (view from bottom of device)
DS33R11 ethernet mapper with integrated t1/e1/j1 transceiver 338 of 338 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entir ely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor re serves the right to change the circuitry and specifications w ithout notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products  printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. 16 revision history revision description 072105 new product release.


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